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參數(shù)資料
| 型號： | MR80C154-25P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 21/232頁 |
| 文件大小： | 61013K |
| 代理商： | MR80C154-25P883 |
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117
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and USIOIE and the
Global Interrupt Enable Flag are set to one the interrupt will be executed immediately. Refer to the USIOIF bit
description on page 116 for further details.
Bits 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used, as shown in Table 15-1 below.
Note:
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion
between the modes of operation.
Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the
mode selected and will always have the same function. The counter and USI Data Register can therefore be
clocked externally and data input sampled, even when outputs are disabled.
Bits 3:2 – USICS[1:0]: Clock Source Select
These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the out-
put is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source
(USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is
transparent and therefore the output is changed immediately.
Clearing the USICS[1:0] bits enables software strobe option. When using this option, writing a one to the USICLK
bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is
no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit.
Table 15-1.
Relationship between USIWM[1:0] and USI Operation
USIWM1
USIWM0
Description
00
Outputs, clock hold, and start detector disabled.
Port pins operates as normal.
01
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORTB register.
However, the corresponding DDRB bit still controls the data direction. When the port pin is
set as input the pin pull-up is controlled by the PORTB bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation.
When operating as master, clock pulses are software generated by toggling the PORTB
register, while the data direction is set to output. The USITC bit in the USICR Register can
be used for this purpose.
10
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins (1).
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-
collector output drives. The output drivers are enabled by setting the corresponding bit for
SDA and SCL in the DDRB register.
When the output driver is enabled for the SDA pin it will force the line SDA low if the
output of the USI Data Register or the corresponding bit in the PORTB register is zero.
Otherwise, the SDA line will not be driven (i.e., it is released). When the SCL pin output
driver is enabled the SCL line will be forced low if the corresponding bit in the PORTB
register is zero, or by the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the output is
enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL
pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
11
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also held low
when a counter overflow occurs, and until the Counter Overflow Flag (USIOIF) is cleared.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MR80C31BH/B | 制造商:n/a 功能描述:8506401XA |
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