參數(shù)資料
型號(hào)： MR80C154-30/883D
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 30 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 39/80頁
文件大?。?/td> 5152K
代理商： MR80C154-30/883D
239
XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 21-6. Start bit sampling.
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. Sample 1 denotes the first zero-sample, as shown in the figure. The clock recovery logic then uses
samples 8, 9, and 10 for normal mode and samples 4, 5, and 6 for double speed mode to decide if a valid start bit is
received. If two or three samples have a low level, the start bit is accepted. The clock recovery unit is synchronized, and
the data recovery can begin. If two or three samples have a high level, the start bit is rejected as a noise spike, and the
receiver looks for the next high-to-low transition. The process is repeated for each start bit.
21.8.2 Asynchronous Data Recovery
The data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit.
Figure 21-7 on page 239 shows the sampling process of data and parity bits.
Figure 21-7. Sampling of data and parity bits.
As for start bit detection, an identical majority voting technique is used on the three center samples for deciding of the
logic level of the received bit. The process is repeated for each bit until a complete frame is received. It includes the first
stop bit, but excludes additional ones. If the sampled stop bit is a 0 value, the frame error (FERR) flag will be set.
Figure 21-8 on page 239 shows the sampling of the stop bit in relation to the earliest possible beginning of the next
frame's start bit.
Figure 21-8. Stop bit and next start bit sampling.
A new high-to-low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For normal speed mode, the first low level sample can be at the point marked (A) in Stop Bit Sampling
and Next Start Bit Sampling. For double speed mode, the first low level must be delayed to point (B). Point (C) marks a
stop bit of full length at nominal baud rate. The early start bit detection influences the operational range of the receiver.
12
34
56
7
8
9
10
11
12
13
14
15
16
12
START
IDLE
0
BIT 0
3
123
4
5
678
12
0
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12
34
56
7
8
9
10
11
12
13
14
15
16
1
BIT n
123
4
5
678
1
RxD
Sample
(CLK2X = 0)
Sample
(CLK2X = 1)
12
34
56
7
8
9
10
0/1
STOP 1
123
4
5
60/1
RxD
Sample
(CLK2X = 0)
Sample
(CLK2X = 1)
(A)
(B)
(C)
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