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| 型號(hào)： | MR80C32-16SHXXX |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 191/219頁(yè) |
| 文件大小： | 7896K |
| 代理商： | MR80C32-16SHXXX |
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71
ATmega8A [DATASHEET]
8159E–AVR–02/2013
16. Timer/Counter0 and Timer/Counter1 Prescalers
16.1
Overview
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different
prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0.
16.2
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fast-
est operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f
CLK_I/O).
Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a fre-
quency of either f
CLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.
16.3
Prescaler Reset
The prescaler is free running (i.e., operates independently of the clock select logic of the Timer/Counter) and it is
shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock
select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example
of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The num-
ber of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.
16.4
External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clk
T1/clkT0). The T1/T0 pin
is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is
then passed through the edge detector. Figure 16-1 shows a functional equivalent block diagram of the T1/T0 syn-
chronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clk
I/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clk
T1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.
Figure 16-1. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T1/T0 pin to the counter is updated.
Tn_sync
(To Clock
Select Logic)
Edge Detector
Synchronization
DQ
LE
DQ
Tn
clk
I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MD80C32EXXX-30/883 | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| MR80C32E-16SC | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52EXXX-20/883D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32E-16SHXXX:R | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52XXX-12SBR | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MR80C32-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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| MR80C32-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MR80C32-36 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MR80C51BH | 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space |
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