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參數(shù)資料
| 型號： | MR80C32E-16SHXXX:R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 149/219頁 |
| 文件大?。?/td> | 7896K |
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33
ATmega8A [DATASHEET]
8159E–AVR–02/2013
the interrupt system to continue operating. This sleep mode basically halts clk
CPU and clkFLASH, while allowing the
other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control
and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conver-
sion starts automatically when this mode is entered.
10.3
ADC Noise Reduction Mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode,
stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial Interface address watch,
Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk
I/O, clkCPU,
and clk
FLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete
interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address
match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, or an external level interrupt on
INT0 or INT1, can wake up the MCU from ADC Noise Reduction mode.
10.4
Power-down Mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this
mode, the External Oscillator is stopped, while the external interrupts, the Two-wire Serial Interface address watch,
and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset,
a Two-wire Serial Interface address match interrupt, or an external level interrupt on INT0 or INT1, can wake up the
MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held
for some time to wake up the MCU. Refer to “External Interrupts” on page 64 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock
10.5
Power-save Mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set, Timer/Counter2 will run during
sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if
the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in
SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-
save mode because the contents of the registers in the asynchronous timer should be considered undefined after
wake-up in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except clk
ASY, allowing operation only of asynchronous modules, includ-
ing Timer/Counter 2 if clocked asynchronously.
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