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參數(shù)資料
| 型號(hào)： | MR80C32E-20/883:RD |
| 廠(chǎng)商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 47/109頁(yè) |
| 文件大?。?/td> | 10824K |
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7593L–AVR–09/12
AT90USB64/128
Figure 24-4. Example with OUT data banks.
24.14 IN Pipe management
The Pipe must be configured first.
When the Host requires data from the device, the firmware has to determine first the IN mode to
use using the INMODE bit:
INMODE = 0. The INRQX register is taken in account. The Host controller will perform
(INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This mode avoids to
have extra IN requests on a Pipe
INMODE = 1. The USB controller will perform infinite IN request until the firmware freezes the
Pipe
The IN request generation will start when the firmware clear the PFREEZE bit.
Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an inter-
rupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the
RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
OUT
DATA
(bank 0)
ACK
TXOUT
FIFOCON
HW
Example with 1 OUT data bank
write data from CPU
BANK 0
Example with 2 OUT data banks
SW
OUT
DATA
(bank 0)
ACK
TXOUT
FIFOCON
write data from CPU
BANK 0
SW
OUT
DATA
(bank 1)
ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
Example with 2 OUT data banks
OUT
DATA
(bank 0)
ACK
TXOUT
FIFOCON
write data from CPU
BANK 0
SW
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
OUT
DATA
(bank 1)
ACK
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| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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