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| 型號(hào)： | MR80C52EXXX-20SCD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 79/219頁(yè) |
| 文件大?。?/td> | 7896K |
| 代理商： | MR80C52EXXX-20SCD |
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17
ATmega8A [DATASHEET]
8159E–AVR–02/2013
Figure 8-3.
On-chip Data SRAM Access Cycles
8.4
EEPROM Data Memory
The Atmel
AVRATmega8A contains 512 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described bellow, specifying the EEPROM
Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 207 contains a detailed description on EEPROM Programming in SPI- or Parallel
Programming mode.
8.4.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-4 on page 20. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC is likely to rise or fall slowly on
Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as mini-
mum for the clock frequency used. See “Preventing EEPROM Corruption” on page 22. for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the
description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When
the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
8.5
I/O Memory
The I/O space definition of the ATmega8A is shown in “” on page 301.
All ATmega8A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT
instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis-
ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set
section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must
clk
WR
RD
Data
Address
Address Valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Vccess Instruction
Next Instruction
相關(guān)PDF資料 |
PDF描述 |
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| MR80C32-16SHXXX | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32EXXX-30/883 | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| MR80C32E-16SC | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52EXXX-20/883D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32E-16SHXXX:R | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
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| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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