參數(shù)資料
型號: MR80C52TXXX-12/883:D
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 233/257頁
文件大?。?/td> 1840K
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁當(dāng)前第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁
77
ATmega8515(L)
2512K–AVR–01/10
External Interrupts
The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The External Interrupts
can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered
interrupt). This is set up as indicated in the specification for the MCU Control Register –
MCUCR and Extended MCU Control Register – EMCUCR. When the External Interrupt
is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger
as long as the pin is held low. Note that recognition of falling or rising edge interrupts on
INT0 and INT1 requires the presence of an I/O clock, described in “Clock Systems and
their Distribution” on page 34. Low level interrupts on INT0/INT1 and the edge interrupt
on INT2 are detected asynchronously. This implies that these interrupts can be used for
waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator
clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25
°C. The
frequency of the Watchdog Oscillator is voltage dependent as shown in “Electrical Char-
acteristics” on page 197. The MCU will wake up if the input has the required level during
this sampling or if it is held until the end of the start-up time. The start-up time is defined
by the SUT Fuses as described in “System Clock and Clock Options” on page 34. If the
level is sampled twice by the Watchdog Oscillator clock but disappears before the end
of the start-up time, the MCU will still wake up, but no interrupt will be generated. The
required level must be held long enough for the MCU to complete the wake up to trigger
the level interrupt.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for interrupt sense control and general
MCU functions.
Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the
corresponding interrupt mask in the GICR are set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 40. The value on the INT1 pin is
sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaran-
teed to generate an interrupt. If low level interrupt is selected, the low level must be held
until the completion of the currently executing instruction to generate an interrupt.
Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
Bit
7654
321
0
SRE
SRW10
SE
SM1
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
0000
000
0
Table 40. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
The low level of INT1 generates an interrupt request.
0
1
Any logical change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
The rising edge of INT1 generates an interrupt request.
相關(guān)PDF資料
PDF描述
MD80C52XXX-12P883D 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MR80C32-12/883:RD 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44
MD80C52TXXX-30:D 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CDIP40
S83C154DXXX-12R 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
MR83C154CXXX-L16P883 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MR80C86 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor
MR80C86/B 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC
MR80C86-2 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor
MR80C86-2/883 制造商:Rochester Electronics LLC 功能描述:- Bulk
MR80C86-2/B 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube