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參數資料
| 型號： | MR82C37A/B |
| 廠商： | INTERSIL CORP |
| 元件分類： | DMA控制器 |
| 英文描述： | 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數： | 6/24頁 |
| 文件大?。?/td> | 430K |
| 代理商： | MR82C37A/B |
14
FN2967.2
March 20, 2006
82C37A
Figure 7 shows an application for a DMA system using the
82C37A DMA controller and the 80C286 Microprocessor.
In this application, the system clock comes from the 82C284
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write
control signals from the 82C288 Bus Controller. The octal
latch for A8-A15 from the DMA controller’s data bus is on the
local 80C286 address bus so that memory chip selects may
still be generated during DMA transfers. The transceiver on
A0-A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow
programming on the upper or lower half of the data bus.
FIGURE 7. 80C286 DMA APPLICATION
MEMW
MEMR
MEMCS
MEMORY
A0 - A23
IOW
DACK
I/O
IOR
SYSTEM
BUS
A0
-
A
7
TRANSCEIVER
OE
T/R
DEVICE
DREQ
CS
D0 - D15
TRANS-
CEIVER
TRANS-
CEIVER
LATCH
STB
OE
AEN
D0-D7
VCC
A0-A7
IOR
IOW
MEMR
MEMW
DACK 0-3
D0-D7
DREQ 0-3
EOP
AEN
ADSTB
HRQ
HLDA
CLK
READY
82C37A
IOR
IOW
MEMR
MEMW
TO CORRESPONDING
82C288 SIGNALS AND
MEMORY/PERIPHERALS
D8
-
D
15
TRANSCEIVER
LATCH
D0
-
D
7
A8
-
A15
DECODE
CHIP SELECT
TO MEMORY/
PERIPHERALS
80C286
A0-A23
D0-D15
READY
HLD
HLDA
CLK
IORC
IOWC
MRDC
MWTC
IOR
IOW
MEMR
MEMW
CLK
82C288
82C284
CLK
PCLK
READY
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