141
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
18.11.6
ASSR – Asynchronous Status Register
Bit 4 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and
an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz XTAL. Writing to EXCLK
should be done before asynchronous operation is selected. Note that the XTAL Oscillator will only run when this bit
is zero.
Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk
I/O. When AS2 is written to one,
Timer/Counter2 is clocked from a XTAL Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the
value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted.
Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCNT2 is ready to be updated with a new value.
Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that OCR2A is ready to be updated with a new value.
Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2A is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated
value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading TCNT2, the actual timer
value is read. When reading OCR2A or TCCR2A, the value in the temporary storage register is read.
18.11.7
GTCCR – General Timer/Counter Control Register
Bit 1 – PSR2: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hard-
ware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the
prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of
chronization mode.
Bit
7
6
5
4
3
2
1
0
(0xB6)
–
EXCLK
AS2
TCN2UB
OCR2UB
TCR2UB
ASSR
Read/Write
RRR
R/W
RRR
Initial Value
0
Bit
7
6
5
4
3
2
1
0
0x23 (0x43)
TSM
–
PSR2
PSR10
GTCCR
Read/Write
R/W
RR
R
R/W
Initial Value
0