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| 型號(hào)： | MR83C154TXXX-12P883R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 17/232頁(yè) |
| 文件大?。?/td> | 61013K |
| 代理商： | MR83C154TXXX-12P883R |
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113
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is com-
pleted. The clock is generated by the master by toggling the USCK pin via the PORTB register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be imple-
mented to control the data flow.
Figure 15-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 15-5), a bus transfer involves the following steps:
1.
The start condition is generated by the master by forcing the SDA low line while keeping the SCL line high
(A). SDA can be forced low either by writing a zero to bit 7 of the USI Data Register, or by setting the cor-
responding bit in the PORTB register to zero. Note that the Data Direction Register bit must be set to one
for the output to be enabled. The start detector logic of the slave device (see Figure 15-6 on page 114)
detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary.
2.
In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this
line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI
Data Register to receive the address. This is done by clearing the start condition flag and resetting the
counter.
3.
The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data
and shifts it into the USI Data Register at the positive edge of the SCL clock.
4.
After eight bits containing slave address and data direction (read or write) have been transferred, the
slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has
addressed, it releases the SCL line and waits for a new start condition.
5.
When the slave is addressed, it holds the SDA line low during the acknowledgment cycle before holding
the SCL line low again (i.e., the USI Counter Register must be set to 14 before releasing SCL at (D)).
Depending on the R/W bit the master or slave enables its output. If the bit is set, a master read operation
is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowl-
edge (E).
6.
Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master
(F), or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last received. When the
master does a read operation it must terminate the operation by forcing the acknowledge bit low after the last byte
transmitted.
15.3.5
Start Condition Detector
The start condition detector is shown in Figure 15-6. The SDA line is delayed (in the range of 50 to 300 ns) to
ensure valid sampling of the SCL line. The start condition detector is only enabled in two-wire mode.
P
S
ADDRESS
1 - 7
8
9
R/W
ACK
1 - 8
9
DATA
ACK
1 - 8
9
DATA
SDA
SCL
A
B
D
E
C
F
相關(guān)PDF資料 |
PDF描述 |
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| MD83C154CXXX-L16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MD83C154XXX-16P883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C154-L16/883 | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154TXXX-16/883 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MR83C154TXXX-20/883 | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
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