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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
18.5.1
Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC2A) bit. Forcing compare match will not set the OCF2A Flag or reload/clear the
timer, but the OC2A pin will be updated as if a real compare match had occurred (the COM2A[1:0] bits settings
define whether the OC2A pin is set, cleared or toggled).
18.5.2
Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR2A to be initialized to the same value as TCNT2
without triggering an interrupt when the Timer/Counter clock is enabled.
18.5.3
Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT2 when using the Output Compare unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM
when the counter is down counting.
The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC2A value is to use the Force Output Compare (FOC2A) strobe bit in Normal
mode. The OC2A Register keeps its value even when changing between Waveform Generation modes.
Be aware that the COM2A[1:0] bits are not double buffered together with the compare value. Changing the
COM2A[1:0] bits will take effect immediately.
18.6
Compare Match Output Unit
The Compare Output mode (COM2A[1:0]) bits have two functions. The Waveform Generator uses the COM2A[1:0]
bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A[1:0] bits control
the OC2A pin output source.
Figure 18-4 shows a simplified schematic of the logic affected by the COM2A[1:0] bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
Port Control Registers (DDR and PORT) that are affected by the COM2A[1:0] bits are shown. When referring to the
OC2A state, the reference is for the internal OC2A Register, not the OC2A pin.