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| 型號(hào)： | MS80C51T-16R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| 文件頁(yè)數(shù)： | 126/170頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | MS80C51T-16R |
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59
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 11-6.
Output Compare Unit, Block Diagram
The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR0x Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x
directly. The content of the OCR0x (Buffer or Compare) Register is only changed by a write operation (the
Timer/Counter does not update this register automatically as the TCNT0 and ICR0 Register). Therefore OCR0x is
not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as
when accessing other 16-bit registers. Writing the OCR0x Registers must be done via the TEMP Register since the
compare of all 16 bits is done continuously. The high byte (OCR0xH) has to be written first. When the high byte I/O
location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCR0xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR0x
buffer or OCR0x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 70.
11.6.1
Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (0x) bit. Forcing compare match will not set the OCF0x flag or reload/clear the timer,
but the OC0x pin will be updated as if a real compare match had occurred (the COM01:0 bits settings define
whether the OC0x pin is set, cleared or toggled).
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
COMnx1:0
WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit)
OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
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