參數(shù)資料
型號(hào)： MS82V16520
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 262,144-Word x 32-Bit x 2-Bank Synchronous Graphics RAM
中文描述： 262,144字× 32位× 2，銀行同步圖形RAM
文件頁(yè)數(shù)： 4/67頁(yè)
文件大?。?/td> 846K
代理商： MS82V16520
4/66
Semiconductor
MS82V16520
PIN DESCRIPTION
*
Notes:
1. When
CS
is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0,
DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by BA (A10).
3. The auto precharge function is enabled or disabled by the A9 input when the read or write command is
issued.
BA (A10)
0
1
Active, read or write
Bank A
Bank B
A9
0
1
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is precharged automatically.
BA
0
0
1
1
0
1
After the end of burst, bank B holds the active status.
After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A9 and BA (A10)
inputs.
A9
0
0
1
BA
0
1
X
Operation
Bank A is precharged.
Bank B is precharged.
Both banks A and B are precharged.
CLK
CS
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 – RA9
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. BA = "L" : Bank A, BA = "H" : Bank B
RAS
CAS
WE
DSF
Functionality depends on the combination. For details, see the function truth table.
DQM0 -
DQM3
DQi
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
Address
BA (A10)
DSF is part of the inputs of graphics command of the MS82V16520.
If DSF is inactive (Low level), MS82V16520 operates just like SDRAM.
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