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參數(shù)資料
| 型號： | MSC1208 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 23-bit x 2 Duplex Controller/Driver with Digital Dimming and Keyscan Function |
| 中文描述： | 23位× 2雙控制器/驅(qū)動器，數(shù)字亮度和鍵盤掃描功能 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 111K |
| 代理商： | MSC1208 |
10/14
MSC1208
Semiconductor
Digital Dimming
The segment and grid ON time can be controlled in the range of 0/1024 (=0%) to 1016/1024
(=99.2%) duty by 10-bit digital dimming data. (See Figure 3, "SEG and GRID Output Timing.")
Data Transfer
The input data (display data or dimming data) from DATA I/O is read into the internal register
after the DATA ENABLE input level changes from "L" to "H". The output data (key switch data)
is output to the DATA I/O pin after the DATA ENABLE input level changes from "H" to "L".
Using this method, bidirectional serial communication using two signal lines, DATA ENABLE
and DATA I/O, can be made.
The transfer data consists of 58 bits including 2-bit parity bit. Data transfer is completed if no
parity error occurs after the 58-bit data has been transferred to the internal register. If a parity
error occurs, the previously transferred data (display data or dimming data) is remained.
If an abnormality occurs in the DATA ENABLE line and no signal pulse is input for 10ms
±
5ms
or more, the data transfer is terminated even if it is in progress. Then, when the next pulse is
input, it is identified as the first pulse.
Diagnositc Function
1. Parity
Bit 57 and bit 58 (PO and PI) of the input data are used for parity check. For the output data,
parity is internally generated to add parity bit to bits 25 and 26.
The parity value is, for both input and output, "P0, P1=1, 1" when a total number of "1"s (or "0"s)
is even, and "P0, P1=0, 0" when it is odd.
2. Default mode
This device enters the default mode if no pulse is input to DATA ENABLE for about 1 second
or if a parity error keeps occurring for about 1 second.
In this mode, at the state of keeping the contents of the dimming data before entering the default
mode, the two segment outputs (SEG1, SEG2) only go ON.
This state is reset if no parity error is detected after the data has been transferred.
3. Self test
When the
TEST
pin is set to a "L" level, all segment outputs go on and off at intervals of about
1 second. At this time, the duty ratio for both segment and grid outputs becomes the maximum
(99.2%).
Power-On Reset
When power is turned on, this device is initialized by the internal power-on reset circuit. Then,
about 1second after the initialization, the device enters the default mode. At this time, the SEG1
and SEG2 segments go ON with the maximum duty ratio (99.2%). This state is reset if no parity
error is detected after the data has been transferred.
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