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參數(shù)資料
| 型號(hào)： | MSC23409C |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 4,194,304-Word x 9-Bit DRAM MODULE : FAST PAGE MODE TYPE |
| 中文描述： | 4194304字× 9位DRAM模塊：快速頁(yè)面模式型 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 255K |
| 代理商： | MSC23409C |
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MSC23409C/CL-xxDS9
Semiconductor
8/13
Notes:
1. A start-up delay of 200
μ
s is required after power-up followed by a minimum of
eight initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before
proper device operation is achieved.
When using the internal refresh counter, a minimum of eight
CAS
before
RAS
initialization cycles is required.
2. AC mesurement assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times are measured between V
IH
and V
IL
.
4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, access time is controlled by t
AA
.
7. t
OFF
(Max.) defines the time at which the output achieves an open circuit condition
and is not referenced to output voltage levels.
8. t
RCH
or t
RRH
must be satisfied for a read cycle.
9. The test mode is initiated by performing a
WE
and
CAS
before
RAS
refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. RA10,
CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data
output pin will indicate a high level. If any internal bits are not equal, then data
output pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operational
state by performing a
RAS
-only refresh cycle or a
CAS
before
RAS
refresh cycle.
10. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC23409CL-XXDS9 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4,194,304-Word x 9-Bit DRAM MODULE : FAST PAGE MODE TYPE |
| MSC2343257A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4,194,304-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO |
| MSC2343257A-XXBS8 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4,194,304-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO |
| MSC2343257A-XXDS8 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4,194,304-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO |
| MSC2343257D | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:4,194,304-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO |
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