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參數(shù)資料
| 型號(hào)： | MSC23S4641E-8BS16 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 4194304 Word x 64 Bit Synchronous Dynamic RAM Module (2BANK)(4M字×64位同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 4194304字× 64位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊（2BANK）（4分字× 64位同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | MSC23S4641E-8BS16 |
MSC23S4641E-8BS16 (98.06.22)
AC CHARACTERISTIC
(VCC = 3.3
±
0.3V, Ta = 0 ~70°C)
Parameter
Symbol
NOTE 1,2 .
Module Spec.
Min.
Max.
8
-
12
-
-
6
-
10
3
-
3
-
2
-
1
-
3
-
-
9
3
-
70
-
20
-
48
100,000
20
-
8
-
20
-
20
-
-
64
10
-
-
3
1
1
2
0
0
CL
3
Unit
Note
Clock Cycle Time
CL=3
CL=2
CL=3
CL=2
tCC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Access Time from Clock
tAC
3,4
3,4
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time(CLK,ADD,DIN)
Input Hold Time(CLK,ADD,DIN)
Output Low Impedance Time from Clock
Output High Impedance Time from Clock
Output Hold from Clock
/RAS Cycle Time
/RAS Precharge Time
/RAS Active Time
/RAS to /CAS Delay Time
Write Recovery Time
Write Command Input Time from Output
/RAS to /RAS Bank Active Delay Time
Refresh Time
Power-down Exit Set-up Time
Input Level Transition Time
/CAS to /CAS Delay Time (Min)
Clock Disable Time from CKE
Data Output High Impedance Time from DQM
Data Input Mask Time from DQMB
Data Input Time from Write Command
Data Output High Inpedance Time
Active Command Input Time from MODE
tCH
tCL
tSI
tHI
tOLZ
tOHZ
tOH
tRC
tRP
tRAS
tRCD
tWR
tOWD
tRRD
tREF
tPDE
tT
ICCD
ICKE
IDOZ
IDOD
IDWD
IROH
IMRD
NOTES:
1) AC measurements assume that tT=1ns.
2) The reference level for timing of input signals is 1.4V.
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(R Load is 50ohm).
4) An access time is measured at 1.4V.
5) If tT is longer than 1ns, the reference level for timing of input signals are V
IH
and V
IL.
OUTPUT
50pF
OUTPUT LOAD
50
1.4v
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