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參數(shù)資料
| 型號(hào)： | MSC23V26457TA-xxBS8 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 2,097,152-Word x 64-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO |
| 中文描述： | 2097152字× 64位DRAM模塊：快速頁(yè)面模式型與江戶 |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | MSC23V26457TA-XXBS8 |
MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8
Semiconductor
641
8
See ADDENDUM K for AC Timing Waveforms
Notes:
1. A start-up delay of 200
μ
s is required after power-up, followed by a minimum of eight
initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before proper device
operation is achieved.
2. The AC characteristics assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, access time is controlled by t
AA
.
7. t
CEZ
(Max.), t
REZ
(Max.), t
WEZ
(Max.) and t
OEZ
(Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They
are included in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.)
the cycle is an early write cycle and the data output pin will remain in a high
impedance state throughout the entire cycle. If t
CWD
≥
t
CWD
(Min.), t
RWD
≥
t
RWD
(Min.), t
AWD
≥
t
AWD
(Min.) and t
CPWD
≥
t
CPWD
(Min.), the cycle is a read modify
write cycle and the data output pin will contain data read from the selected cell. If
neither conditions is satisfied, the data output logic state (at access time) is
undefined.
11. These parameters are referenced to
CAS
leading edge in an early write cycle and to
WE
leading edge in an
OE
control write cycle or a read modify write cycle.
12. The test mode is initiated by performing a
WE
and
CAS
before
RAS
refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
In the test mode CA9 is not used and each DQ pin now accesses 2 bit locations. In
a read cycle, if the 2 data bits are equal, the DQ pin will indicate a high level. If the
2 data bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a
RAS
-only refresh cycle or a
CAS
before
RAS
refresh cycle.
13. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
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