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MSC5301B-02
Semiconductor
12/15
Multiple Configuration
This LCD driver can form multiple configuration.
It is possible to form a maximum of 4 devices (a panel of up to 256
¥
8 dots in size can be formed)
by using chip select signals CS0 and CS1. The devices in multiple configuration must be
synchronized with one another. In this configuration, one device in the master mode, where the
original oscillation signal
f
and the synchronous signal FRAM are output, and the other devices
in the slave mode, where the original oscillation signal
f
and the synchronous signal FRAM are
input, are used in combination.
Refer to items CS0 and CS1 of the pin description on the mode setting method.
The original oscillation signal output pin
f
of the master mode devices is connected to the OS1
pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the
FRAM pin of the slave mode device.
Connect SI,
SCK
, LATCH, A/
D
, POR and BLK of the master mode devices to SI,
SCK
, LATCH,
A/
D
, POR and BLK of each of the slave mode devices and connect them to CPU for control.
In addition, connect the devices so that V
DSP
, V
1
, V
2
, V
3
, V
4
and GND are shared between the
devices, and connect them to each voltage level divided by resistors.
Address Data Configuration
The lower address, which is the address of the display RAM, corresponds to the common sides
C0 - C7 of LCD panel. Dummy data 1 must be always set to "H".
The upper address corresponds to the logical state of chip select pins CS0 and CS1 and lower
address is set to the chip only with which corresponded.
For the chip to output the common signal (
f
, FRAM), set both of the upper address 2 bits to "L".
The 2 bits of dummy data can be set to either "L" or "H".
7
6
5
4
3
2
1
0
Dummy data 2
DM2
Upper address
CS1
Lower address
A1
2 bits
2 bits
(MSB)
(LSB)
3 bits
1 bit
Dummy data 1
DM0
DM1
CS0
A2
A0