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    參數(shù)資料
    

    


    


    
型號(hào)：
MSC7110VM800

    

    
廠商：
FREESCALE SEMICONDUCTOR INC

    

    
元件分類：
顯示控制器

    

    
英文描述：
FLUORESCENT DSPL CTRL, PBGA400

    

    
封裝：
17 X 17 MM, LEAD FREE, BGA-400

    

    
文件頁(yè)數(shù)：
40/56頁(yè)

    

    
文件大?。?/td>
702K

    

    
代理商：
MSC7110VM800


    

    

    

	
    
    
    

    
    
	
    Hardware Design Considerations
    MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
    Freescale Semiconductor
    45
    3.2.3
    Power Planes
    Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board power supply. Each GND pin
    should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
    The MSC7110 VDDC power supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and
    associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor
    lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
    for DDR Controller power guidelines.
    3.2.4
    Decoupling
    Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
    values of 0.01
    μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
    should consist of a 0.01 F high frequency capacitor with low effective series resistance (ESR) and effective series inductance
    (ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling
    capacitors, one 10
    μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7110 voltage pins.
    Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.
    3.2.5
    PLL Power Supply Filtering
    The MSC7110 VDDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
    power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. VDDPLL
    can be connected to VDDC through a 2 Ω resistor. VSSPLL can be tied directly to the GND plane. A circuit similar to the one
    shown in Figure 31 is recommended. The PLL loop filter should be placed as closely as possible to the VDDPLL pin (which are
    located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 F capacitor should
    be closest to VDDPLL, followed by the 0.1 F capacitor, the 10 F capacitor, and finally the 2-Ω resistor to VDDC. These traces
    should be kept short.
    3.2.6
    Power Consumption
    You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
    Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
    Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
    AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
    Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, HDI16, TDM,
    UART, I2C, and timer modules.
    For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
    Figure 31. PLL Power Supply Filter Circuits
    VDDC
    VDDPLL
    2
    Ω
    0.1 F 0.01 F
    10 F
    Because
    of
    an
    order
    from
    the
    United
    States
    International
    Trade
    Commission,
    BGA-packaged
    product
    lines
    and
    part
    numbers
    indicated
    here
    currently
    are
    not
    available
    from
    Freescale
    for
    import
    or
    sale
    in
    the
    United
    States
    prior
    to
    September
    2010:
    MSC711XADS
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
MSC7110VM1000
FLUORESCENT DSPL CTRL, PBGA400

    

    
MSC7118VF1200
0-BIT, 300 MHz, OTHER DSP, PBGA400

    

    
MSC8101M1250F
64-BIT, 62.5 MHz, OTHER DSP, PBGA332

    

    
MSC8101M1500F
64-BIT, 75 MHz, OTHER DSP, PBGA332

    

    
MSC8101VT1250F
64-BIT, 62.5 MHz, OTHER DSP, PBGA332

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
MSC7112-01
 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:12-Segment x 16-Digit or 16-Segment x12-Digit Display Controller/Driver

    

    
MSC7112VF1000
功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA

    

    
MSC7112VM1000
功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA

    

    
MSC7112VM800
功能描述:IC DSP PROCESSOR 16BIT 400MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤

    

    
MSC7113VF1000
功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA

    

    
    
    
    
	
    	
    
    
     
     
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