參數(shù)資料
型號: MSC7113VM1000
廠商: Freescale Semiconductor
文件頁數(shù): 54/60頁
文件大?。?/td> 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: StarCore
類型: 定點
接口: 主機接口,I²C,UART
時鐘速率: 266MHz
非易失內(nèi)存: ROM(8 kB)
芯片上RAM: 208kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤
MSC7113 Data Sheet, Rev. 11
Revision History
Freescale Semiconductor
58
7
Revision History
Table 36 provides a revision history for this data sheet.
Table 36. Document Revision History
Revision
Date
Description
0
Apr 2004
Initial public release.
1
May 2004
Added ordering information and new package options.
2
Aug. 2004
Updated clock parameter values.
Updated DDR timing specifications.
Updated I2C timing specifications.
3
Sep. 2004
Updated Figures 1-2 and 1-2 to correct HDSP and DBREQ.
Corrected EE0 port reference.
Updated ball location for HDSP.
4
Jan. 2005
Added signal HA3.
Updated absolute maximum ratings, DDR DRAM capacitance specifications, clock parameters, reset
timing, and TDM timing.
Added note for timing reference for I2C interface.
Expanded GPIO timing information.
Corrected pin T20 and K20 signal designation.
Corrected signal names to GPAO15 and IRQ2.
Expanded design guidelines in Chapter 4.
5
Mar. 2005
Updated features list.
Updated power specifications.
Changed CLKIN frequency range.
Added clock configuration information.
Updated JTAG timings.
6
Apr. 2005
Added recommended power supply ratings and updated equations to estimate power consumption.
7
Oct. 2005
Updated core and total power consumption examples.
8
Dec. 2005
Added information about signals GPIOA16, GPIOA17, GPIOA27, GPIOA28, and GPIOA29 to signal
description and pinout location lists.
9
Nov. 2006
Updated Reference Manual reference to MSC711x Reference Manual.
Updated arrows in Host DMA Writing Timing figure.
Updated boot overview.
10
Aug. 2007
Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.
Added a note to clarify the definition of TCK timing 700 in new Table 31.
The power-up and power-down sequences have been expanded to five possible design scenarios/cases.
These cases replace the previously recommended power-up/power-down sequence recommendations. The
section has been clarified by adding subsection headings.
11
Apr 2008
Change the PLL filter resistor from 20
Ω to 2 Ω in Section 3.2.5.
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