參數(shù)資料
型號(hào): MSC7115VF1000
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 11/56頁(yè)
文件大小: 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: StarCore
類(lèi)型: SC1400 內(nèi)核
接口: 主機(jī)接口,I²C,UART
時(shí)鐘速率: 266MHz
非易失內(nèi)存: 外部
芯片上RAM: 400kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤(pán)
Specifications
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
19
This section describes the DC electrical characteristics for the MSC7115.
Note:
The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO
and VDDC vary by +2 percent or both vary by –2 percent).
Table 6 lists the DDR DRAM capacitance.
Table 5. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
Core and PLL voltage
VDDC
VDDPLL
1.14
1.2
1.26
V
DRAM interface I/O voltage1
VDDM
2.375
2.5
2.625
V
I/O voltage
VDDIO
3.135
3.3
3.465
V
DRAM interface I/O reference voltage2
VREF
0.49
× VDDM
1.25
0.51
× VDDM
V
DRAM interface I/O termination voltage3
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high CLKIN voltage
VIHCLK
2.4
3.0
3.465
V
DRAM interface input high I/O voltage
VIHM
VREF + 0.28
VDDM
VDDM + 0.3
V
DRAM interface input low I/O voltage
VILM
–0.3
GND
VREF – 0.18
V
Input leakage current, VIN = VDDIO
IIN
–1.0
0.09
1
A
VREF input leakage current
IVREF
——
5
A
Tri-state (high impedance off state) leakage current,
VIN = VDDIO
IOZ
–1.0
0.09
1
A
Signal low input current, VIL = 0.4 V
IL
–1.0
0.09
1
A
Signal high input current, VIH = 2.0 V
IH
–1.0
0.09
1
A
Output high voltage, IOH = –2 mA, except open drain pins
VOH
2.0
3.0
V
Output low voltage, IOL= 5 mA
VOL
—0
0.4
V
Typical core power5
at 200 MHz
at 266 MHz (mask set 1M88B only)
PC
222
293
mW
Notes:
1.
The value of VDDM at the MSC7115 device must remain within 50 mV of VDDM at the DRAM device at all times.
2.
VREF must be equal to 50% of VDDM and track VDDM variations as measured at the receiver. Peak-to-peak noise must not
exceed ±2% of the DC value.
3.
VTT is not applied directly to the MSC7115 device. It is the level measured at the far end signal termination. It should be equal
to VREF. This rail should track variations in the DC level of VREF.
4.
Output leakage for the memory interface is measured with all outputs disabled, 0 V
≤ VOUT ≤ VDDM.
5.
The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 200 MHz or 266 MHz, 1.2 V
core).
Table 6. DDR DRAM Capacitance
Parameter/Condition
Symbol
Max
Unit
Input/output capacitance: DQ, DQS
CIO
30
pF
Delta input/output capacitance: DQ, DQS
CDIO
30
pF
Note:
These values were measured under the following conditions:
VDDM = 2.5 V ± 0.125 V
f = 1 MHz
TA = 25°C
VOUT = VDDM/2
VOUT (peak to peak) = 0.2 V
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