參數(shù)資料
型號: MSC8144EVT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 64/80頁
文件大小: 1251K
代理商: MSC8144EVT800B
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
67
4.
NC indicates “not connected” and means do not connect anything to the pin.
5.
The phrase “in use” indicates a typical pin connection for the required function.
Note:
Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
3.4.1
DDR Memory Related Pins
This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.
Note:
For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines
of strobes in DDR1), please refer to Table 51.
3.4.1.1
DDR Interface Is Not Used
Table 51. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name
Pin Connection
MDQ[0–31]
NC
MDQS[0–3]
NC
MDQS[0–3]
NC
MA[0–15]
NC
MCK[0–2]
NC
MCK[0–2]
NC
MCS[0–1]
NC
MDM[0–3]
NC
MBA[0–2]
NC
MCAS
NC
MCKE[0–1]
NC
MODT[0–1]
NC
MDIC[0–1]
NC
MRAS
NC
MWE
NC
MECC[0–7]
NC
ECC_MDM
NC
ECC_MDQS
NC
ECC_MDQS
NC
MVREF
GND
VDDDDR
GND
Note:
If the DDR controller is not used, disable the internal DDR clock by writing a 1 to the CLK11DIS bit in the System Clock Control
Register (SCCR[CLK!11DIS]). See Chapter 7, Clocks, in the MSC8144E Reference Manual for details.
相關(guān)PDF資料
PDF描述
MSC8144ETVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144VT800B 133 MHz, OTHER DSP, PBGA783
MSC8144SVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144TVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144SVT1000B 133 MHz, OTHER DSP, PBGA783
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