參數(shù)資料
型號: MSC8144SVT1000A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 54/80頁
文件大小: 1250K
代理商: MSC8144SVT1000A
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
58
Figure 30. SMII Mode Signal Timing
2.6.10.6
RGMII AC Timing Specifications
Table 45 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 46 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 45. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKEWT
-0.5
0.5
ns
Data to clock input skew (at receiver) 2
tSKEWR
0.9
2.6
ns
Notes:
1.
At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2.
This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is
added to the associated clock signal.
3.
GCR4 should be programmed as 0x00001004.
Table 46. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKEWT
–2.6
–0.9
ns
Data to clock input skew (at receiver) 2
tSKEWR
–0.5
0.5
ns
Notes:
1.
At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2.
This implies that PC board design will require clocks to be routed with no additional trace delay
3.
GCR4 should be programmed as 0x0004C130.
Valid
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD
Valid
tSMXR
tSMDXKH
tSMDVKH
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