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參數(shù)資料
| 型號： | MSC8144TVT1000A |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件頁數(shù)： | 76/80頁 |
| 文件大?。?/td> | 1250K |
| 代理商： | MSC8144TVT1000A |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Revision History
Freescale Semiconductor
78
7
Revision History
Table 66 provides a revision history for this data sheet.
Rev.
Date
Description
0
Feb. 2007
Initial public release.
1
Apr. 2007
Adds new I/O multiplexing mode 7 that supports POS functionality.
Updates reference voltage supply for pins G5, H7, and H8 in Table 1.
Updates start-up timing recommendations with regard to TRST and M3_RESET in Section 2.7.1.
Adds input clock duty cycles in Table 20.
Updates PCI AC timings in Table 41.
Removes UTOPIA internal clock specifications in Table 52.
Updates JTAG timings in Table 56.
Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4.
Miscellaneous pin connectivity guidelines were updated in Table 71.
Updates name of core subsystem reference manual.
2
June 2007
Corrected AA4 definition in Table 1. Changed TDM5TD3 to correct name TDM5TDAT.
Removed Figure 35 because the device does not support UTOPIA using an internal clock. Renumbered
subsequent figures.
Removed Section 3.5 Thermal Considerations. To be replaced with an application note.
3
Sep 2007
Updated M3 voltage range in Table 3.
Changed note in Table 7 for PLL power supplies.
DDR voltage designator changed from VDD to VDDDDR in Table 8, Table 10, Section 2.7.4.1, Section 2.7.4.2,
and Figure 11. Changed range on IOZ in Table 8 and Table 10.
Deleted Section 2.6.5 on page 32 and renumbered subsequent subsections.
Deleted text before new Section 2.6.5.1.
Added a 1 to the note in Table 15 and added note 1 to input pin capacitance.
Deleted ac voltage rows from Table 16. Added note 1 to input pin capacitance.
Changed output high and low voltage levels in Table 17 and Table 18.
Deleted text before Table 19.
Added clock skew ranges in percent in Table 21.
Changed VREF to MVREF in Table 26.
Changed VDD to VDDIO in Table 41 Updated note 2.
Added note 4 to Table 42. Changed tTDMSHOX value.
Changed VDD to VDDGE in Figure 27 and Figure 30.
Changed the value of the data to clock out skew in Table 51.
Changed EE pin timing in Table 55.
Changed the head for the JTAG timing section, now Section 2.7.15.
Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in Table 56.
Added new Section 3.3 with guidelines for board layout for clock and timing signals. Renumbered subsequent
sections.
4
Sep 2007
Changed leakage current values in Table 13, Table 14, Table 11, Table 16, Table 17, Table 18, and Table 19
from –10 and 10
μa to –30 and 30 μa.
Updated note 1 in Table 45.
5
Oct 2007
Updated SPI signal names in Table 1.
6
Oct 2007
Updated SPI signal names in Table 1.
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PDF描述 |
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| MSC8144SVT1000B | 133 MHz, OTHER DSP, PBGA783 |
| MSC8144VT1000A | 133 MHz, OTHER DSP, PBGA783 |
| MSC8144SVT800A | 133 MHz, OTHER DSP, PBGA783 |
| MSC8156SVT1000B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8254TVT800B | 0-BIT, OTHER DSP, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8144TVT1000B | 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144TVT800A | 功能描述:IC DSP QUAD 800MHZ 783FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8144TVT800B | 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144VT1000A | 功能描述:IC DSP QUAD 1GHZ 783FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8144VT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-Bit 1GHz 1000MIPS 783-Pin FCBGA 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA 制造商:Freescale 功能描述:DSP 32-Bit 1GHz 1000MIPS 783-Pin FCBGA |
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