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參數(shù)資料
| 型號： | MSM5117805D |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 2,097,152-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| 中文描述： | 2097152字× 8位動態(tài)隨機存儲器：快速頁面模式型與江戶 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MSM5117805D |
MSM5117805D
8/14
Notes:
1.
A start-up delay of 200
m
s is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2.
The AC characteristics assume t
T
= 2ns.
3.
V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals. Transition
times (t
T
) are measured between V
IH
and V
IL
.
4.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5.
Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.)
limit, then the access time is controlled by t
CAC
.
6.
Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.)
limit, then the access time is controlled by t
AA
.
7.
t
CEZ
(Max), t
REZ
(Max), t
WEZ
(Max), t
OEZ
(Max) define the time at which the output achived the
open circuit condition and are not referenced to output voltage levels.
8.
t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9.
t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If t
WCS
3
t
WCS
(Min.), then the cycle is an early write
cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If
t
CWD
3
t
CWD
(Min.), t
RWD
3
t
RWD
(Min.), t
AWD
3
t
AWD
(Min.) and t
CPWD
3
t
CPWD
(Min.), then the cycle
is a read modify write cycle and data out will contain data read from the selected cell; if neither
of the above sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a
low level. The test mode is cleared and the memory device returned to its normal operating state
by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
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| MSM5117805F-50TS-K | 2,097,152-Word 】 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM5117805F | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5117805F-50JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:2,097,152-Word 】 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5117805F-50TS-K | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:2,097,152-Word 】 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5117805F-60JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5117805F-60TS-K | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
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