參數(shù)資料
型號： MSM514252A-10ZS
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 262,144-Word x 4-Bit Multiport DRAM
中文描述： 262,144字× 4位多端口內(nèi)存
文件頁數(shù)： 27/33頁
文件大?。?/td> 358K
代理商： MSM514252A-10ZS
MSM514252A
Semiconductor
27/33
Write Mask Data/Data Input and Output: W1/IO1 - W4/IO4
W1/IO1 - W4/IO4 have the functions of both Input/Output and a control input signal. As the
standard DRAM’s I/O pins, input data on the W1/IO1 - W4/IO4 are written into the RAM port
during the write cycle. The input data is latched at the falling edge of either
CAS
or
WB
/
WE
,
whichever occurs later. The RAM data out buffers, which will output read data from the W1/
IO1-W4/IO4 pins, become low impedance state after the specified access times from
RAS
,
CAS
,
DT
/
OE
and column address are satisfied and the output data will remain valid as long as
CAS
and
DT
/
OE
are kept "low". The outputs will return to the high-impedance state at the rising edge
of either
CAS
or
DT
/
OE
, whichever occurs earlier.
In addition to the conventional I/O functions, the W1/IO1 - W4/IO4 have the function to set the
mask data, which select mask input pins out of four inputs pins, W1/IO1 - W4/IO4, at the falling
edge of
RAS
. Data is written in to the DRAM on data lines where the write-mask data is a logic
"1". Writing is inhibited on data lines where the write-mask data is a logic "0". The write-mask
data is valid for only one cycle.
Serial Clock: SC
SC is a main serial cycle control input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC.
In a serial read, the output data becomes valid on the SIO pins after the maximum specified serial
access time t
SCA
from the rising edge of SC.
The serial clock SC also increments the 9 bits serial pointer which is used to select the SAM
address. The pointer address is incremented in a wrap-around mode to select sequential
locations after the setting location which is determined by the column address in the read transfer
cycle. When the pointer reaches the most significant address location (decimal 511), the next SC
clock will place it at the least significant address location (decimal 0).
The serial clock SC must be held data constant V
IH
or V
IL
level during read/pseudo write/write
transfer operations and should not be clocked while the SAM port is in the standby mode to
prevent the SAM pointer from being incremented.
Serial Enable:
SE
The
SE
is a serial access enable control and serial read/write control input signal. In a serial read
cycle,
SE
is used as an output control. In a serial write cycle,
SE
is used as a write enable control.
When
SE
is "high", serial access is disable, however, the serial address pointer location is still
incremented when SC is clocked even when
SE
is "high".
Serial Input/Output: SIO1 - SIO4
Serial input/output mode is determined by the most recent read, write or pseudo write transfer
cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write
or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input
mode.
相關(guān)PDF資料
PDF描述
MSM514252A 262,144-Word x 4-Bit Multiport DRAM
MSM514256C-70RS 262,144-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM514256C 262,144-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM514260C 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM514260CSL 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM514252A-70JS 制造商:ROHM Semiconductor 功能描述:
MSM514252A-80ZS 制造商:ROHM Semiconductor 功能描述:
MSM514256B-60J 制造商:OK International 功能描述:
MSM514256C 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,144-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM514256C-70RS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,144-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
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