參數(shù)資料
型號: MSM52V1001LL
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 131,072-Word ×8-Bit CMOS STATIC RAM(128k字×8位靜態(tài)RAM)
中文描述: 131,072詞× 8位的CMOS靜態(tài)RAM(128K的字× 8位靜態(tài)RAM)的
文件頁數(shù): 6/11頁
文件大?。?/td> 158K
代理商: MSM52V1001LL
Semiconductor
MSM52V1001LL
6/11
Read Cycle
OE
to Output in Low-Z
Output Hold Time from Address Change
OE
to Output in High-Z
OE
Access Time
Parameter
Symbol
MSM52V1001LL-10
Min.
100
MSM52V1001LL-12
Min.
120
Unit
Max.
100
100
100
50
35
35
35
Max.
120
120
120
60
35
35
35
Read Cycle Time
Address Access Time
CE
1
, CE
2
Access Time
CE
1
, CE
2
to Output in Low-Z
CE
1
, CE
2
to Output in High-Z
ns
ns
ns
ns
10
10
5
10
10
10
5
10
ns
ns
ns
ns
ns
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
OH
t
CHZ1
t
CHZ2
t
OHZ
(V
CC
= 2.7 V to 3.6 V, Ta = 0°C to 70°C)
ADDRESS
CE
1
CE
2
OE
D
OUT
t
RC
t
AA
t
CHZ1
t
CO1
t
CLZ1
t
CO2
t
CLZ2
t
CHZ2
t
OE
t
OHZ
t
OLZ
Valid Data-out
t
OH
Notes:
1. A read cycle occurs during the overlap of
CE
1
= "L", CE
2
= "H",
OE
= "L" and
WE
= "H".
2. t
CLZ1
and t
CLZ2
are specified from
CE
1
= "L" or CE
2
= "H", whichever occurs last.
3. t
CHZ1
and t
CHZ2
are specified from
CE
1
= "H" or CE
2
= "L", whichever occurs first.
4. t
OHZ
, t
CHZ1
and t
CHZ2
are specified by the time when DATA is floating, not defined by
the output level.
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