- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378678 > MSM5416263 (OKI SEMICONDUCTOR CO., LTD.) 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MSM5416263 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動態(tài)RAM) |
| 中文描述： | 262,144字× 16位多端口內(nèi)存（256k字× 16位多端口動態(tài)RAM）的 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MSM5416263 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Semiconductor
MSM5416263
28/40
PIN FUNCTIONS
Address Input: A0 - A8
The 18 address bits decode 16 bits of the 4,194,304 locations in the MSM5416263 memory array.
The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row
address bits are latched at the falling edge of
RAS
. The following 9 column address bits are
latched at the falling edge of
CAS
.
Row Address Strobe:
RAS
RAS
is a basic RAM control signal. The RAM port is in standby mode when the
RAS
level is
"high". As the standard DRAM’s
RAS
signal function,
RAS
is the control input that latches the
row address bits, and a random access cycle begins at the falling edge of
RAS
.
In addition to the conventional
RAS
signal function, the level of the input signals
CAS
,
TRG
,
WEL
,
WEU
and DSF at the falling edge of
RAS
, determines the MSM5416263 operation mode.
Column Address Strobe:
CAS
As the standard DRAM’s
CAS
signal function,
CAS
is the control input signal that latches the
column address input, and the state of the special function input DSF to select in conjunction with
the
RAS
control, either read/write operations or the special block write feature on the RAM port
when the DSF is held "low" at the falling edge of
RAS
.
CAS
also acts as a RAM port output enable signal.
Data Transfer/Output Enable:
TRG
TRG
is also a control input signal having multiple functions. As the standard DRAM’s
OE
signal
function,
TRG
is used as an output enable control when
TRG
is "high" at the falling edge of
RAS
.
In addition to the conventional
OE
signal function, a data transfer operation is started between
the RAM port and the SAM port when
TRG
is "low" at the falling edge of
RAS
.
Write Per Bit/Write Enable:
WEL
and
WEU
WEL
and
WEU
are control input signals having multiple functions. As the standard DRAM’s
WE
signal function, these are used to write data into the memory on the RAM port when
WEL
and
WEU
are both "high" at the falling edge of
RAS
.
In addition to the conventional
WE
signal function, both
WEL
and
WEU
determine the write-per-
bit function, when either
WEL
or
WEU
is "low" at the falling edge of
RAS
during RAM port
operations.
The
WEL
and
WEU
also determine the direction of data transfer between the RAM and SAM.
When both
WEL
and
WEU
are "high" at the falling edge of
RAS
, the data is transferred from RAM
to SAM (read transfer). When either
WEL
or
WEU
is "low" at the falling edge of
RAS
, the data
is transferred SAM to RAM (write transfer).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM548128BL | 131,072-Word ×8-Bit High-Speed PSRAM(128k字×8位高速偽靜態(tài)RAM) |
| MSM548332 | 278,400-Word×12-Bit Field Memory(278,400字×12位場存儲器) |
| MSM54V32126A | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM54V32126A-45GS-K | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM54V32126A-45TS-K | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM5416263-60G3-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416263-60GS-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416273-50G3-K | 制造商:ROHM Semiconductor 功能描述:DUE TO FLOOD DAMAGE TO TESTERS |
| MSM5416273-50GS-K | 制造商:ROHM Semiconductor 功能描述: 制造商:OK International 功能描述:256K X 16 VIDEO DRAM, 50 ns, PDSO64 |
| MSM541627360GSK | 制造商:OK International 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。