參數(shù)資料
型號(hào)： MSM6222B-01GS-L
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 顯示控制器
英文描述： 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 5/45頁(yè)
文件大?。?/td> 487K
代理商： MSM6222B-01GS-L
MSM6222B-01
Semiconductor
13/45
FEDL6222B-01-01
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfere with the internal operation caused by LCD driving. Consequently, when data is
written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
(1) Correspondence between address and display position in the 1-line display mode
When the MSM6222B-01 alone is used, up to 8 characters can be displayed from the
first to eighth digit.
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
00
First
digit
(Display)
01
2
02
3
03
4
04
5
4E
79
4F
80
Leftmost position
Rightmost position
Display position
DD RAM address (hex.)
00
First
digit
01
2
02
3
03
4
04
5
05
6
06
7
07
8
4F
First
digit
00
2
01
3
02
4
03
5
04
6
05
7
06
8
(Display
shifted
to right)
First
digit
02
2
03
3
04
4
05
5
06
6
07
7
08
8
(Display
shifted
to left)
01
LSB
MSB
DB0
DB6
ADC
(HEX)
L
2A
(Example)
When DD RAM
address is 2A
HLHLH
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