參數(shù)資料
型號(hào): MSM6255GS-K
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 顯示控制器
英文描述: 128 X 256 CHARACTERS DOT MAT LCD DSPL CTLR, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù): 39/40頁(yè)
文件大?。?/td> 474K
代理商: MSM6255GS-K
MSM6255
Semiconductor
7/39
TIMING DIAGRAM
LCDC Control Signal Timing Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock Cycle Time
tCP
180
ns
Clock "H" Level Pulse Width
PWH
80
ns
Clock "L" Level Pulse Width
PWL
80
ns
Clock Rise/Fall Time
tcr/tcf
——20
ns
Character Clock Delay Time
tCH
200
ns
Memory Address Clock Delay Time
tMA
100
ns
Memory Address Disable Delay Time
tAD1
——40
ns
Memory Address Enable Delay Time
tAD2
——40
ns
CPU Address Delay Time
tAD3
100
ns
Refresh Address Delay Time
tAD4
100
ns
Reset "H" Level Pulse Width
tRES
1—
m
s
CPU Address Delay Time
tAD5
100
ns
(CL = 30pF, VDD = 5V ± 5%, Ta = –20 to +85°C)
tCP
PWL
PWH
tcr
tcf
tCH
tMA
Upper Side Address
Lower Side Address
VALID
Floating
tAD1
tAD2
Refresh Address
CPU Address
Refresh Address
tAD3
tAD4
tRES
tAD5
XT
(External clock)
CHφ
MA0 - MA15
ADF
MA0 - MA15
RA0 - RA3
MA0 - MA15
DIEN
RES
A0 - A15
MA0 - MA15
tAD5
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