參數(shù)資料
型號(hào): MSM6404A-XXXGS-2K
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù): 15/26頁(yè)
文件大?。?/td> 252K
代理商: MSM6404A-XXXGS-2K
21/25
MSM6404A/6404VS
Semiconductor
Differences between MSM6404A and MSM6404VS (PIGGYBACK)
Item
MSM6404A
MSM6404VS (Piggyback)
1.
Ports P0, 1, 3 are set to "1" and ports P2, 4,
5, 6, 7, 8 are reset to "0" directly by the reset
input signal.
Ports P0, 1, 3 are set to "1" and ports P2, 4,
5, 6, 7, 8 are initialized during reset cycle.
After being reset, the timer continues to stop
until data is set in it.
It is undefined whether the timer starts or
not after being reset. Therefore, the timer
should be initialized by software.
Serial out F/F (SOF/F) is set to "0" after being
reset.
It is undefined whether serial out F/F
(SOF/F) is "0" or "1" after being reset.
Therefore the serial out F/F should be
initialized by software.
Port
initialization
during reset
2. Timer
operation
3. Shift register
Internal clock
Port
input/output
timing
4.
Input
Data are input
at this time.
Input
Data are input
at this time.
Internal clock
Synchronized
with falling edge
Data are output
at this time.
Data are output
at this time.
Output
TTL FO = "1"
(IOL = 1.6 mA @ 0.4 V)
LSTTL FO = "1"
(IOL = 0.4 mA @ 0.4 V)
Port
input/output
characteristics
5.
P2.0-3
VDD
VDD VDD
TTL compatible input
CMOS input
P0.0-P8.3
(Except P2.0-3)
Up to 4 Kbytes
Up to 8 Kbytes accessible
Available ROM
capacity
Not available
Available
LJP a13, LCAL a13
instruction
Internal clock
Output
6.
7.
相關(guān)PDF資料
PDF描述
MSM6404VS 4-BIT, 4.2 MHz, MICROCONTROLLER, CDIP42
MSM6404A-XXXRS 4-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PDIP42
MSM6404A-XXXGS-K 4-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP44
MSM6408-XXXGS-2K 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
MSM6408-XXXGS-K 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
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參數(shù)描述
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