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Semiconductor
MSM64162D
FUNCTIONAL DESCRIPTION
A/D converter (ADC)
The MSM64162D has a built-in 1-channel RC oscillation type A/D converter. The A/D converter
is composed of a 1-channel oscillation circuit, Counter A (CNTA0-4, a 4.8-digit decade counter),
Counter B (CNTB0-3, a 14-bit binary counter), and A/D Converter Control Registers 0 and 1
(ADCON0, ADCON1).
By counting oscillation frequencies that vary depending on a resistor or capacitor connected to
the RC oscillation circuit, the A/D converter converts resistance values or capacitance values to
corresponding digital values. By using a thermistor or humidity sensor as a resistance, a
thermometer or a hygrometer can be constructed.
LCD driver (LCD)
The MSM64162D has a built-in LCD driver for 24 outputs.
The LCD driver consists of 21 4-bit display registers (DSPR0-20), the Display Control Register
(DSPCON), a 24-output LCD driver circuit, and a bias generation circuit (BIAS).
There are three types of driving methods: 1/4 duty, 1/3 duty and 1/2 duty. Software selects the
duty mode.
A mask option can select either a common driver or a segment driver for each LCD driver pin.
A mask option can also specify assignment of each bit of the display register to each segment.
All the display registers must be selected by a mask option.
L16 to L23 of the LCD driver can be configured to be output ports by a mask option.
The relationship between the duty, the bias method, and the maximum segment number follows:
1/4 duty 1/3 bias method ------- 80 segments
1/3 duty 1/3 bias method ------- 63 segments
1/2 duty 1/2 bias method ------- 44 segments
Buzzer driver (BD)
The MSM64162D has a built-in buzzer driver with 2 buzzer output frequencies and 4 buzzer
output modes. Each buzzer output is selected by the Buzzer Control Register (BDCON) and the
Buzzer Frequency Control Register (BFCON).
Capture circuit (CAPR)
The MSM64162D captures 32 Hz to 256 Hz output of the time base counter at the falling of Port
0.0 or 0.1 (P0.0 or P0.1) to "L" level when the pull-up resistor input is chosen, or at the rising to
"H" level when the pull-down resistor input is chosen. The capture circuit is composed of the
Capture Control Register (CAPCON) and the Capture Registers (CAPR0, CAPR1) that fetch
output from the time base counter.
Watchdog timer (WDT)
The MSM64162D has a built-in watchdog timer to detect CPU malfunction. The watchdog timer
is composed of a 6-bit watchdog timer counter (WDTC) to count a 16 Hz output and a watchdog
timer control register (WDTCON) to reset WDTC.