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Semiconductor
MSM64164C
Watchdog timer (WDT)
The MSM64164C has a built-in watchdog timer to detect CPU malfunction. The watchdog timer
is composed of a 6-bit watchdog timer counter (WDTC) to count a 16 Hz output and a watchdog
timer control register (WDTCON) to reset WDTC.
Clock generation circuit (2CLK)
The clock generation circuit (2CLK) in the MSM64164C contains a 32.768 kHz crystal oscillation
circuit, a 400 kHz RC oscillation circuit, and a clock control port. This circuit generates the system
clock (CLK) and the time base clock (32.768 kHz).
The system clock drives the CPU while the time base clock drives the time base counter and the
buzzer driver.
Via the contents of the frequency Control Register (FCON), the system clock can be switched
between 32.768 kHz (the output of the crystal oscillation circuit) and 400 kHz (the output of the
RC oscillation circuit).
Note: The oscillation frequency of the RC oscillation circuit varies depending on the value of
an external resistor (ROS), operating power supply voltage (VDD), and ambient
temperatures (Ta).
Time base counter (TBC)
The MSM64164C has a built-in time base counter (TBC) that generates clocks to be supplied to
internal peripheral circuits. The time base counter is composed of 15 binary counters and a 1/
10 frequency dividing circuit. The count clock of the time base is driven by the oscillation clock
(32.768 kHz) of the crystal oscillation circuit. The output of the time base counter is used for the
buzzer driver, the system reset circuit, the watchdog timer, the time base interrupt, the sampling
clocks of each port, and the capture circuit.
I/O port
Input-output ports (P2, P3, P4) (12 bits) : Pull-up (pull-down) resistor input or high-
impedance input, CMOS output or NMOS
open drain output: these can be specified for
each bit; external 0 interrupt
Input port (P0) (4 bits)
: Pull-up (pull-down) resistor input or high-
impedance input; external 1 interrupt
Output port (P1) (4 bits)
: CMOS output or NMOS open drain output
Interrupt (INTC)
The MSM64164C has ten interrupt sources (10 vector addresses), of which two are external
interrupts from ports and eight are internal interrupts.
Of the ten interrupt sources, only the watchdog interrupt cannot be disabled (non-maskable
interrupt). The other nine interrupts are controlled by the master interrupt enable flag (MI) and
the interrupt enable registers (IE0, IE1 and IE2). When an interrupt condition is met, the CPU
branches to a vector address corresponding to the interrupt source.