參數(shù)資料
型號(hào): MSM6542-03GS-VK
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO24
封裝: 0.430 INCH, PLASTIC, SOP-24
文件頁(yè)數(shù): 43/54頁(yè)
文件大?。?/td> 406K
代理商: MSM6542-03GS-VK
Semiconductor
MSM6542-010/2/03
115
[Setting interrupt conditions]
Perfomr the following setting with the DP bit set at 0. The set values are independent of the
setting of the DP bit.
(a) Periodic interrupt output (*1)
(b) Alarm interrup output (*1)
* 2
* 3
CD register
IT/PLS1
1
MASK1
1
Set CD' register
(*, CY2, CY1,
CY0)
Dummy readout of CE register
CD register
IT/PLS1
1
MASK1
0
*1
From the viewpoint of software, the IRQ FLAG
1
bit is used. From the viewpoint of hardware, pin
1 (PERIODIC OUT) is used for the MSM6542-
03 or pin 1 (INTERRUPT OUT) for the MSM6542-
01/02.
*2
For the MSM6542-1/2, a signal resulting from
the ORing with output triggered by an alarm is
output to pin 1. When alarm factors are not
required, the MASK
2 bit must be set at 1.
*3
The IRQ FLAG
1 bit is cleared.
*1
From the viewpoint of software, the IRQ FLAG
2
bit is used. From the viewpoint of hardware, pin
3 (ALARM OUT) is used for the MSM6542-03
or pin 1 (INTERRUPT OUT) for the MSM6542-
01/02.
*2
For the MSM6542-01/02, a signal resulting
from the ORing with output triggered by a
periodic carry is output to pin 1. When periodic
factors are not required, 1 must be set in the
MASK
1 bit.
*3
Time required to output the previous interrupt
factors
*4
The IRQ FLAG
2 bit is cleared.
CD register
IT/PLS2
1
MASK2
1
Set A-S1 to A-M1O
and A-W
* 2
* 3
* 4
Idling for 185 s
Set A-ENABLE register
Dummy readout of CE register
CD register
IT/PLS2
1
MASK2
0
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