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參數(shù)資料
| 型號(hào)： | MSM65524A-XXXJS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | 0.950 INCH, 1.27 MM PITCH, PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 8/27頁(yè) |
| 文件大?。?/td> | 202K |
| 代理商： | MSM65524A-XXXJS |
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Semiconductor
MSM65524A/65P524
AC Characteristics
External memory control
(VDD=AVDD=VRH=2.7 to 5.5V, GND=AGND=VRL=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
Clock Period
tC
100
—
"L" Clock Pulse Width
tCLW
45
—
"H" Clock Pulse Width
tCHW
CL=100pF
45
—
ALE Pulse Width
tAW
tC+tCHW–20
—
ALE Pulse Delay Time 1
tALD1
tCLW–20
—
ALE Pulse Delay Time 2
tALD2
tCLW–20
—
RD Pulse Width
tRW
tC+tCHW–20
—
RD Pulse Delay Time
tRD
tCLW–20
tCLW+20
WR Pulse Width
tWW
tC+tCHW–40
—
WR Pulse Delay Time
tWD
tCLW–20
tCLW+40
"L" Address Setup Time
tLAS
tC–40
—
"H" Address Setup Time
tHAS
tC–40
—
"L" Address Hold Time
tLAH
tCLW–20
—
Bus Float Time
tLAZ
—20
"H" Address Hold Time
tHAHR
tC–20
—
"H" Address Hold Time
tHAHW
tC–20
—
Read Data Access Time
tRDAA
—tC+tCLW–15
Read Data Access Time
tRDAR
—tCHW+10
Read Data Hold Time
tRDH
0—
Write Data Setup Time
tWDS
tC+tCHW–40
—
Write Data Hold Time
tWDH
tCLW–20
—
VDD=4.5 to 5.5V
Clock Period
tC
200
—
"L" Clock Pulse Width
tCLW
90
—
"H" Clock Pulse Width
tCHW
90
—
VDD=2.7 to 5.5V
ns
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