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參數(shù)資料
| 型號： | MSM6636BGS-AK |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 41.6K bps, LOCAL AREA NETWORK CONTROLLER, PDSO30 |
| 封裝： | 5.60 MM, 0.65 MM PITCH, PLASTIC, SSOP-30 |
| 文件頁數(shù)： | 14/73頁 |
| 文件大?。?/td> | 646K |
| 代理商： | MSM6636BGS-AK |
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MSM6636/6636B User’s Manual
Internal Register Details
3 – 5
3.5 Receive Data Length Register
—
RL3
RL2
RL1
RL0
MSB
LSB
2 0
... Receive Data Length
Shows the byte length of receive data stored to the receive buffer (excluding CRC).
“—” indicates bits that are not provided. They will always read “0”.
3.6 Initialization/Read Completion Indication Register
—
MSB
LSB
2 1
... Completion Command
Shows the completion of initialization after reset by writing to register 21H.
Shows by writing to register 21H that CPU has read all receive data stored to the receive register. Data to be
written is not specified.
3.7 Interrupt Request Flag
LEN
ABN
D-P OVER CRC FORM INV
IFS
MSB
LSB
2 2
Flags related to message abnormality etc.
BUSY NOACK NRSP
—
BRK RSP RCV
TR
MSB
LSB
2 3
Flags related to message transmit/receive status etc.
PAR*
— WAKR WAKD BPG BPV BNG BNV
MSB
LSB
2 4
*
In MSM6636B, this bit is “—”.
Flags related to LAN bus line etc.
“1” indicates that a corresponding interrupt occurred. Each bit is cleared by writing “0” to it. All bits are
automatically set to “0” at reset. For details of how to clear, see Section 5.4, “CPU Interrupt Function” (page
5-3).
The bits to which a flag is not allocated will always read “0”.
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