參數(shù)資料
型號(hào)： MSM66Q587TS-K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 172K
代理商： MSM66Q587TS-K
5/24
Semiconductor
MSM66585/586/587/P587/Q587
PIN DESCRIPTIONS
Symbol
Type
Description
P0_0-P0_7/
AD0-AD7
I/O
P1_0-P1_7/
A8-A15
I/O
P2_0-P2_3
P2_4-P2_5/
RT08-RT09
P2_6-P2_7
I/O
P4_0/ETMCK
P4_1-P4_7
I/O
P5_4/PSEN
P5_5/ALE
I/O
Port 0 is 8 input/output pins. Input or output can be specified for each bit with the
Port 0 Mode Register (P0IO). Pull-up resistors can be specified for each bit with the
Port 0 Pull-Up Register (P0PUP).
These pins also function as time-multiplexed address outputs and data input/output
pins (AD0-AD7) when accessing memory that has been expanded externally
(program or data memory).
After reset (by RES signal input, BRK instruction execution, or op code trap), P0 will
be high-impedance inputs.
Port 1 is 8 input/output pins. Input or output can be specified for each bit with the
Port 1 Mode Register (P1IO). Pull-up resistors can be specified for each bit with the
Port 1 Pull-Up Register (P1PUP).
P1_0-P1_7 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 1 Secondary Function
Control Register (P1SF). The input/output settings by P1IO will be ignored for pins
that have been set to the secondary function by P1SF.
These pins function as output pins for address A8-A15 when accessing program
memory or data memory that has been expanded externally. When the EA pin is low,
A8-A15 will be output regardless of P1SF settings.
After reset (by RES signal input, BRK instruction execution, or op code trap), P1 will
be high-impedance inputs.
P2_4 and P2_5 also have a secondary function as input/output pins for internal operation.
Their secondary function can be set for each bit with the Port 2 Secondary Function
Control Register (P2SF). The input/output settings of P2IO will be ignored for pins
that have been set to the secondary function by P2SF.
These pins output a previously set level when the value of Timer Registers 8 and 9
match a selected counter value.
After reset (by RES signal input, BRK instruction execution, or op code trap), P2 will
be high-impedance inputs.
Port 4 is 8 input/output pins. Input or output can be specified for each bit with the
Port 4 Mode Register (P4IO). Pull-up resistors can be specified for each bit with the
Port 4 Pull-Up Register (P4PUP).
P4_0 also has a secondary function as an input pin for internal operation. Its secondary
function can be set for the bit with the Port 4 Secondary Function Control Register (P4SF).
The input/output settings by P4IO will be ignored for pins that have been set to the
secondary function by P4SF.
This is the external clock input pin for the counter of a general 8-bit timer.
After reset (by RES signal input, BRK instruction execution, or op code trap), P4 will
be high-impedance inputs.
Port 5 is 2 input/output pins. Input or output can be specified for each bit with the
Port 5 Mode Register (P5IO).
P5_4 and P5_5 also have a secondary function as output pins for internal operation.
Their secondary function can be set for each bit with the Port 5 Secondary Function
Control Register (P5SF). The input/output settings of P5IO will be ignored for pins
that have been set to the secondary function by P5SF.
PSEN (P5_4):
This pin outputs the strobe signal for read operations when external program memory
is accessed. Operation will automatically switch to the secondary function when the
EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low.
ALE (P5_5):
This pin outputs the strobe for externally latching the lower 8 address bits output from
P0 when external memory is accessed. Operation will automatically switch to the
secondary function when the EA pin is low. This pin will be pulled up when both the
EA pin and RESET pin are low.
After reset (by RES signal input, BRK instruction execution, or op code trap), P5 will
be high-impedance inputs.
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