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參數(shù)資料
| 型號(hào)： | MSM7564-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 198K |
| 代理商： | MSM7564-01 |
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Semiconductor
MSM7564-01
7
CPU Interfaces
Symbol
CPUTYPE
STCHG
CS0, 1
ALE
RD
Description
CPU Type Select
CPUTYPE selects CPU bus type of ADA7 - 0 and AOD7 - 0.
'1' : 80 mode (multiplexed address and data bus for Intel-compatible)
'0' : 68 mode (separated address and data bus for Motorola-compatible)
Status Change Output
When interface memory registers (0C, 0D, 1E, 1F) change, STCHG is set to "0". When
the registers are read by external CPU, this pin is set to '1'.
Chip Select Input 0 and 1
When CS0 and CS1 are set to '1', this chip is selected for microprocessor operation.
Address Latch Enable Input
ALE allows the microprocessor to latch the address bus (ADA7 - 0) when CPUTYPE is
80 mode. Address bus is latched at the falling edge of ALE.
Read Enable
RD
is active LOW and is used to read from internal memory register via 8-bit address
data input/output pins selected by CPUTYPE pin. CS0 and CS1 must be high.
Write Enable
WR
is active Low and is used to write the data at the rising edge via data input/output
pins selected by CPUTYPE pin into internal memory registers. CS0 and CS1 must be
high.
8 bit Address and Data Bus 1
8 lines provide 2 modes of bus type which are selected by CPUTYPE pin. AD7 to 0 are
controlled by ALE,
RD
and
WR
.
80 mode : (I/O) address input and data input/output
68 mode : (I) address input
8 bit Address and Data Bus 2
8 lines provide 2 modes of bus type which are selected by CPUTYPE pin. AD7 to 0 are
controlled by ALE,
RD
and
WR
.
80 mode : (O) address output (outputs latched address by ALE)
68 mode : (I/O) address input/output
Type
I
O
I
I
I
WR
I
ADA7 - 0
I/O
AOD7 - 0
I/O
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|---|---|
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