參數(shù)資料
型號: MSM7575
廠商: OKI SEMICONDUCTOR CO., LTD.
元件分類: Codec
英文描述: Multi-Function ADPCM CODEC(多功能ADPCM(自適應(yīng)差分脈沖編碼調(diào)制)編碼譯碼器)
中文描述: 多功能差分PcM編解碼器(多功能差分PcM(自適應(yīng)差分脈沖編碼調(diào)制)編碼譯碼器)
文件頁數(shù): 6/25頁
文件大?。?/td> 187K
代理商: MSM7575
6/25
Semiconductor
MSM7575
SG, SGB
Analog signal ground output.
The output voltage is about 1.4 V. The bypass capacitors (10
μ
F in parallel with 0.1
μ
F ceramic
type) should be put between this pin and AG to get the specified noise characteristics. This
output voltage is 0 V during power-down.
AG
Analog ground.
DG
Digital ground.
This ground is separated from the analog signal ground(AG) in this device. The DG pin must be
kept as close to the AG pin possible on the PCB.
V
DD
+3 V power supply.
PDN/RESET
Power down and reset control input.
“L” level makes the whole chip enter to power down state, and, at the same time, all of control
register data are reset to the initial state. Set this pin to “H” level during normal operating mode.
The power down state is controlled by a logical OR with CR0-B5 of the control register. When
using the pin
PDN/RESET
for the power down and reset control, CR0-B5 should be set to digital
“0”.
MCK
Master clock input.
The frequency must be 9.6 MHz or 19.2 MHz. The applied clock frequency is selected by the
control register data CR0-B6. The master clock signal is allowed to be asynchronous with BCLK,
XSYNC, and RSYNC.
PCMSO
Transmit PCM data output.
This PCM output signal is output from MSB in synchronization with the rising edge of BCLK or
XSYNC. A pull-up resistor must be connected to this pin, because this output is configuared as
an open drain.
During power down, this output is at high impedance state.
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