
Semiconductor
MSM7603/7603B
10/20
AC Characteristics
Parameter
Clock Frequency
When Internal Sync Signal is not used
Clock Cycle Time
When Internal Sync Signal is not used
Clock Duty Ratio
Clock "H" Level Pulse Width
fc = 19.2 MHz
Clock "L" Level Pulse Width
fc = 19.2 MHz
Clock Rise Time
Clock Fall Time
Sync Clock Output Time
Internal Sync Clock Frequency
Internal Sync Clock Output Cycle Time
Internal Sync Clock Duty Ratio
Internal Sync Signal Output Delay Time
Internal Sync Signal Period
Internal Sync Signal Output Width
Transmit/Receive Sync Clock Frequency
Transmit/Receive Sync Clock Cycle Time
Transmit/Receive Sync Clock Duty Ratio
Transmit/Receive Sync Signal Period
Sync Timing
Sync Signal Width
Receive Signal Setup Time
Receive Signal Hold Time
Receive Data Input Time
Serial Output Delay Time
Symbol
f
C
t
MCK
t
DMC
t
MCH
t
MCL
t
r
t
f
t
DCM
f
CO
t
CO
t
DCO
t
DCC
t
CYO
t
WSO
f
SCK
t
SCK
t
DSC
t
CYC
t
XS
t
SX
t
WSY
t
DS
t
DH
t
ID
t
SD
t
XD
t
WR
t
DRS
t
DRE
t
DIT
t
DPS
t
DPE
Min.
—
17.5
—
50.0
40
20.8
20.8
—
—
—
—
—
—
64
0.488
40
123
45
45
t
SCK
45
45
—
—
—
1
5
—
Typ.
19.2
—
52.08
—
—
—
—
256
3.9
50
—
125
t
CO
—
—
50
125
—
—
—
—
—
7t
SCK
—
—
—
—
—
Max.
—
20.0
—
57.14
60
31.3
31.3
—
—
—
5
—
—
2048
15.6
60
—
—
t
CYC
-t
SCK
—
—
—
—
90
90
—
—
52
Min.
—
17.5
—
50.0
40
20.8
20.8
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
t
SCK
45
45
—
—
—
1
5
—
100
—
—
10
Typ.
19.2
—
52.08
—
—
—
—
—
—
—
256
3.9
50
—
125
t
CO
—
—
50
125
—
—
—
—
—
7t
SCK
—
—
—
—
—
—
—
—
—
Max.
—
20.0
—
57.14
60
31.3
31.3
5
5
40
—
—
—
5
—
—
2048
15.6
60
—
—
t
CYC
-t
SCK
—
—
—
—
90
90
—
—
52
—
111
15
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
kHz
m
s
%
ns
m
s
m
s
kHz
m
s
%
m
s
ns
ns
m
s
ns
ns
m
s
ns
ns
m
s
ns
ns
m
s
ns
ns
ns
V
DD
= 2.7 V to 3.6 V
V
DD
= 4.5 V to 5.5 V
(Ta = –40C to +85C)
Reset Start Time
Reset End Time
Processing Operation Start Time
Power Down Start Time
Power Down End Time
Reset Pulse Width Immediately after Power Down
t
WPR
100
—
—
10
—
—
—
—
—
111
15
—
Reset Signal Input Width
Control Pin Hold Time (
RST
)
Control Pin Setup Time
Control Pin Hold Time
t
DHR
t
DTS
t
DTH
20
0
160
—
—
—
—
—
—
ns
ns
ns
Control Pin Setup Time (
RST
)
t
DSR
20
—
—
ns
—
—
—
—
—
—
5
5
40
20
0
160
20
—
—
—
—
—
—
—
—