參數(shù)資料
型號(hào)： MSM7708-02
廠商： OKI SEMICONDUCTOR CO., LTD.
元件分類(lèi)： Codec
英文描述： Serial Register Interface ADPCM CODEC for Telephone Recording(用于電話(huà)記錄的串行寄存器接口ADPCM編碼譯碼器)
中文描述： 串行接口差分PcM注冊(cè)解碼器的電話(huà)錄音（用于電話(huà)記錄的串行寄存器接口差分PcM編碼譯碼器）
文件頁(yè)數(shù)： 8/38頁(yè)
文件大?。?/td> 232K
代理商： MSM7708-02
Semiconductor
MSM7708-02
8/38
SGT, SGR
Outputs of the analog signal ground voltage.
SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the same
for the receive system. The output voltage value is approximately 1.4 V. Connect bypass 10
m
F
and 0.1
m
F (ceramic type) capacitors between these pins and the AG pin. To reduce the response
time of the receiver power on, it is recommended to apply 1
m
F and 0.1
m
F bypass capacitors.
During power down, the output changes to 0 V.
V
DD
Power supply.
DG, AG
Ground.
DG is the digital system ground. AG is the analog system ground. Since DG and AG are separated
in the device, connect them as close as possible on the circuit board.
PDN
Power down control input.
When set to a digital "0", the system changes to the power down state and control register is not
reset. Since the power down mode is controlled by CRC0 - B5 of the control register ORed with
the signal from the
PDN
pin, set CRC0 - B5 to digital "0" when using this pin.
RESET
Reset control input of the CODEC control register.
When set to digital "0," each bit of the control register is reset and the internal circuit changes to
the power down state. During normal operation, set this pin to digital "1".
MCK
Master clock input.
The clock frequency is 19.2 MHz. MCK can be asynchronous with XSYNC, RSYNC, and BCLK.
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