參數(shù)資料
型號: MSM7730
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 2M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 PITCH, PLASTIC, LQFP-144
文件頁數(shù): 19/20頁
文件大?。?/td> 179K
代理商: MSM7730
s MSM7730 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
6
Oki Semiconductor
MODEM Interface
The MSM7730 provides Frequency Hopping Physical Layer Convergence Protocol (FH PLCP) framing
and the FH modem as defined by the IEEE 802.11 specification. The radio synthesizer control pins are
used for all modem options. A diagnostic port is provided when the internal modem is used. Several
options are provided by the internal FH modem. The following table shows the pin usage for the various
modem options.
Modulator
The MSM7730 provides an integrated 24-MHz internal digital IF modulator. The modulator generates
ordinary Frequency Shift Keying (CP-FSK) and relies on radio filtering to shape this to Gaussian Fre-
quency Shift Keying (GFSK). Since the radio requires a SAW filter to achieve out-of-band transmit
requirements, this filter can also be used to provide the required in-band frequency response. This pro-
vides for more efficient power consumption because extra digital filtering is not required in the modula-
tor. The modulator is shown in Figure 4.
The modulator supports two modes of modulator operation:
1-Mbps, 2-ary CP-FSK
2-Mbps, 4-ary CP-FSK
The modulation scheme for 1-Mbps operation is Gaussian Frequency Shift Keying (GFSK). The modula-
tion scheme for 2-Mbps operation is 4-level GFSK.
Deviations can be set independently for both modes. Modes switch phase continuously in a single clock
cycle.
1-Mb deviation: 1MDEV = N x 326 /4096 Hz
2-Mb deviation: 2MDEV = N x 3 x 326/4096 Hz
where N = 0.63.
Modem Options and Pin Connections [1]
1.
All modem signals are synchronized to RCK.
Modem Interface
FH Mbps (Low Cost)
FH 1/2 Mbps (Normal ADC)
FH 1/2 Mbps (Delta ADC)
MSEL
1
2
3
IFD[5:0]
IFD[5:0] to TXIF DAC
IFD[4] carries SLICE on RX
IFD[5:0] to TXIF
DAC and IFD[3:0] from RXADC
IFD[5:0] to TXIF DAC (also used for Delta ADC)
RXD
Baseband RX data from radio
Recovered data (Debug out)
Input from Delta ADC comparator
PHY
RADIO
Input
Processing
Modulator
Ramp
Processing
State Machine
TxData
TxClkEn
IFData
Mode
ModeEn
Figure 4. Modulator Block Diagram
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