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Semiconductor
MSM7731-01
(11) CR10 (Echo canceler I/O level settings)
B7, B6 ... Acoustic output level control
These bits control the PAD level of the gain of the acoustic echo canceler's SoutA
output. PAD is turned ON or OFF by either the
GLPADTHR
pin or the
GLPADTHR
control register bit (CR1-B2). It is recommended to set the level to
the positive level equal to LPADA2 and LPADA1.
(0, 1) : +18 dB
(0, 0) : +12 dB
(1, 1) : +6 dB
(1, 0) :
0 dB
B5, B4 ... Acoustic input level control
These bits control the PAD level of the loss of the acoustic echo canceler's SinA
input. PAD is turned ON or OFF by either the
GLPADTHR
pin or the
GLPADTHR
control register bit (CR1-B2). Set the level such that echo return
loss (value of returned echo) will be attenuated.
(0, 1) : –18 dB
(0, 0) : –12 dB
(1, 1) : –6 dB
(1, 0) :
0 dB
B3, B2 ... Line output level control
These bits control the PAD level of the gain of the line echo canceler's SoutL
output. PAD is turned ON or OFF by either the
GLPADTHR
pin or the
GLPADTHR
control register bit (CR1-B2). It is recommended to set the level to
the positive level equal to LPADL2 and LPADL1.
(0, 1) : +18 dB
(0, 0) : +12 dB
(1, 1) : +6 dB
(1, 0) :
0 dB
B1, B0 ... Line input level control
These bits control the PAD level of the loss of the line echo canceler's SinL
output. PAD is turned ON or OFF by either the
GLPADTHR
pin or the
GLPADTHR
control register bit (CR1-B2). Set the level such that echo return
loss (value of returned echo) will be attenuated.
(0, 1) : –18 dB
(0, 0) : –12 dB
(1, 1) : –6 dB
(1, 0) :
0 dB
B7
GPADA2
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
CR10
Initial value
GPADA1
LPADA2
LPADA1
GPADL2
GPADL1
LPADL2
LPADL1