參數(shù)資料
型號(hào): MSM80C154SJS
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, 24 MHz, MICROCONTROLLER, PQCC44
封裝: 0.650 INCH, 1.27 MM PITCH, PLASTIC, QFJ-44
文件頁(yè)數(shù): 26/41頁(yè)
文件大小: 274K
代理商: MSM80C154SJS
31/40
MSM80C154S/83C154S
Semiconductor
(3) External data memory access AC characteristics
*1 The variable check is from 0 to 24 MHz when the external check is used.
*2 For 2.2VCC<4 V
Parameter
Symbol
Unit
Min.
Max.
1 to 24 MHz
Variable clock from
41.7
1000
ns
tCLCL
XTAL1, XTAL2 Oscillator Cycle
2tCLCL-40
ns
tLHLL
ALE Signal Width
1tCLCL-15
ns
tAVLL
Address Setup Time
(to ALE Falling Edge)
1tCLCL-35
ns
tLLAX
Address Hold Time
(from ALE Falling Edge)
6tCLCL-100
ns
tRLRL
RD Signal Width
6tCLCL-100
ns
tWLWH
WR Signal Width
—5tCLCL-105
ns
tRLDV
RAM Data Read Time
(from RD Signal Falling Edge)
0—
ns
tRHDX
RAM Data Read Hold Time
(from RD Signal Rising Edge)
—2tCLCL-70
ns
tRHDZ
Data Bus Floating Time
(from RD Signal Rising Edge)
—8tCLCL-100
ns
tLLDV
RAM Data Read Time
(from ALE Signal Falling Edge)
—9tCLCL-105
ns
tAVDV
RAM Data Read Time
(from Address Output)
3tCLCL-40
3tCLCL+40
ns
tLLWL
RD/WR Output Time from ALE
Falling Edge
4tCLCL-70
ns
tAVWL
RD/WR Output Time from Address
Output
1tCLCL-40
ns
tQVWX
WR Output Time from Data Output
7tCLCL-105
ns
tQVWH
Time from Data to WR Rising Edge
2tCLCL-50
ns
tWHQX
Data Hold Time
(from WR Rising Edge)
0—
ns
tRLAZ
Time from to Address Float RD
Output
1tCLCL-30
1tCLCL+40
ns
tWHLH
Time from RD/WR Rising Edge to
ALE Rising Edge
*1
3tCLCL-100
*2
1tCLCL+100
VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C
PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load
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