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參數(shù)資料
| 型號： | MSM80C49-XXXGS-2K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 11 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 169K |
| 代理商： | MSM80C49-XXXGS-2K |
18/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
4.3 Hardware power-down mode
In the MSM80C48, MSM80C49 and MSM80C50, forcing the level at the VDD pin to a "0"
during either external ROM or internal ROM mode results in suspension of the oscillator
function and subsequent floating (high impedance) of all the I/O pins except the RESET,
SS and XTAL 1/2 pins. The CPU is thereby stopped while maintaining internal status.
4.4 Cancellation of hardware power-down mode
(1) Use of RESET pin
m
The clock generator is activated and the CPU started up when a "1" level is applied to
the VDD pin while a "0" level is input to the RESET pin. If this "0" level is kept applied
to the RESET pin until oscillation become stable, the CPU will be reset and will start
executing from address 0.
(2) Use of the INT pin during external interrupt enable status (i.e. following execution of EN
I instruction)
m
The clock generator is activated and the CPU started up when a "1" level is applied to
the VDD pin while a "0" level is applied to the INT pin. If this "0" level is maintained
until the occurrence of at least 2 ALE output signals, an external interrupt is generated,
and execution starts from address 3.
However, if the power-down mode is started during an interrupt processing routine,
execution will be continued on the next instruction after the present instruction.
(3) Use of the INT pin during external interrupt disable mode (i.e. following excution of DIS
I instruction or hardware reset)
m
The clock generator is activated and the CPU started up when a "1" level is applied to
the VDD pin while a "0" level is applied to the INT pin. If this "0" level is maintained
until the occurrence of at least 2 ALE output signals, execution is continued on the next
instruction after the present instruction.
(4) Use of VDD pin only
m
The clock generator is activated and the CPU started up when a "1" level is applied to
the VDD pin while a "1" level is also applied to both the RESET and INT pins. In this
case, execution is resumed from the stopped position.
相關PDF資料 |
PDF描述 |
|---|---|
| MSM80C48-XXXGS-2K | 8-BIT, MROM, 11 MHz, MICROCONTROLLER, PQFP44 |
| MSM80C50-XXXRS | 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP40 |
| MSM80C49-XXXRS | 8-BIT, MROM, 11 MHz, MICROCONTROLLER, PDIP40 |
| MSM80C51-RS | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| MSM80C51F-GS-K | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM80C50 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:CMOS 8-Bit Microcontroller |
| MSM80C51F | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:CMOS 8-Bit Microcontroller |
| MSM80C85 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
| MSM80C85A-2RS | 制造商:OKI Semiconductor 功能描述:Microprocessor, 8 Bit, 40 Pin, Ceramic, DIP |
| MSM80C85AH | 制造商:OK International 功能描述: |
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