參數(shù)資料
型號(hào): MSM80C85AHGS
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 8-Bit CMOS MICROPROCESSOR
中文描述: 8位CMOS微處理器
文件頁(yè)數(shù): 5/29頁(yè)
文件大?。?/td> 210K
代理商: MSM80C85AHGS
5/29
Semiconductor
MSM80C85AHRS/GS/JS
Name
Address Branched To (1)
When Interrupt Occurs
24H
Type Trigger
RST 7.5
RST 6.5
RST 5.5
INTR
3CH
34H
2CH
(2)
Rising edge (latched).
High level unitl sampled.
High level until sampled.
High level until sampled.
TRAP
Priority
2
3
4
5
1
Rising edge and high level unit sampled.
Table 1 Interrupt Priority, Restart Address, and Sensitivity
Notes: (1) The processor pushes the PC on the stack before branching to the indicated
address.
(2) The address branched to depends on the instruction provided to the cpu
when the interrupt is acknowledged.
RESET IN
(Input)
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release
power down mode. The data and address buses and the control lines are 3-stated during RESET and
because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be
altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing
connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as
long as RESET IN is applied.
Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to
the processor clock and lasts an integral number of clock periods.
X
1
and X
2
are connected to a crystal to drive the internal clock generator. X
1
can also be an external
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal
operating frequency.
Symbol
Function
RESET OUT
(Output)
X
1
, X
2
(Input)
SID
(Input)
SOD
(Output)
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
is executed.
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
V
CC
GND
+ 5 Volt supply
Ground Reference.
CLK
(Output)
Clock Output for use as a system clock. The period of CLK is twice the X
1
, X
2
input period.
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