參數(shù)資料
型號(hào): MSM80C85AHJS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, 5 MHz, MICROPROCESSOR, PQCC44
封裝: PLASTIC, QFJ-44
文件頁(yè)數(shù): 30/31頁(yè)
文件大?。?/td> 427K
代理商: MSM80C85AHJS
8
Semiconductor
MSM80C85AHRS/GS/JS
DRIVING THE X1 AND X2 INPUTS
You may drive the clock inputs of the MSM80C85AH with a crystal, or an external clock source.
The driving frequency must be at least 1 MHz, and must be twice the desired internal clock
frequency; hence, the MSM80C85AH is operated with a 6 MHz crystal (for 3 MHz clock). If a
crystal is used, it must have the following characteristics:
Parallel resonance at twice the clock frequency desired
CL (load capacitance) 30 pF
CS (shunt capacitance) 7 pF
RS (equivalent shunt resistance) 75 ohms
Drive level: 10 mW
Frequency tolerance:
±0.05% (suggested)
Note the use of the capacitors between X1, X2 and ground. These capacitors are required to
assure oscillator startup at the correct frequency.
Figure 4 shows the recommended clock driver circuits. Note in B that a pull-up resistor is
required to assure that the high level voltage of the input is at least 4 V.
For driving frequencies up to and including 6 MHz you may supply the driving signal to X, and
leave X2 open-circuited (Figure 4B). To prevent self-oscillation of the MSM80C85AH, be sure
that X2 is not coupled back to X1 through the driving circuit.
Note:
Since the constant values may vary depending on oscillator, consult the manufacturer
of the oscillator used when designing a circuit.
Figure 4 Clock Driver Circuits
X1
CINT = 15 pF
X2
C1
C2
X1
X2
* X2 Left Floating
VIH > 0.8 VCC
High time > 40 ns
Low time > 40 ns
33 pF Capacitor required for crystal frequency 10 to 6.25 MHz
50 pF Capacitor required for crystal frequency 6.25 to 4 MHz
100 pF Capacitor required for crystal frequency <4 MHz
MSM80C85AH
A. Quartz Crystal Clock Driver
B. 1 - 10 MHz Input Frequency External
Clock Drive Circuit
*
相關(guān)PDF資料
PDF描述
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