參數(shù)資料
型號(hào)： MSM82C51A-2GS-K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32
封裝： PLASTIC, SSOP-32
文件頁(yè)數(shù)： 10/26頁(yè)
文件大小： 188K
代理商： MSM82C51A-2GS-K
18/26
Semiconductor
MSM82C51A-2RS/GS/JS
Receiver Control and Flag Timing (SYNC Mode)
x x x x x x 0 1 2 3 4
0 1 2 3 4
x x x x x x x
0 1 2 3 4
0 1 x 3 4
SYNDET
(Pin) (Note 1)
SYNDET (SB)
OVERRUN
ERROR (SB)
RXRDY (PIN)
C/D
WR
RD
RXD
RXC
Don't
Care
SYNC
CHAR 1
SYNC
CHAR 2
Data
CHAR 1
Data
CHAR 2
Data
CHAR 3
SYNC
CHAR 1
SYNC
CHAR 2
Don't Care
Data
CHAR 1
Data
CHAR 2
ETC
CHAR ASSY Begins
Exit Hunt Mode
Set SYNDET
Exit Hunt Mode
Set SYNDET (Status bit)
CHAR ASSY
Begins
Wr EH
RxEn
Rd Data
CHAR 1
Rd Status
Wr Err Res
Rd Data
CHAR 3
Rd SYNC
CHAR 1
Rd Status
Wr EHo
Rd Status
Data
CHAR2
Lost
tIS
tES
(Note 2)
Note:
PAR
1. Internal Synchronization is based on the case of 5 data bit length + parity bit and 2 synchronous charactor.
2. External Synchronization is based on the case of 5 data bit length + parity bit.
Note: 1. Half-bit processing for the start bit
When the MSM82C51A-2 is used in the asynchronous mode, some problems are
caused in the processing for the start bit whose length is smaller than the 1-data bit
length. (See Fig. 1.)
2. Parity flag after a break signal is received (See Fig. 2.)
When the MSM82C51A-2 is used in the asynchrous mode, a parity flag may be set
when the next normal data is read after a break signal is received.
A parity flag is set when the rising edge of the break signal (end of the break signal)
is changed between the final data bit and the parity bit, through a RXRDY signal may
not be outputted.
If this occurs, the parity flag is left set when the next normal dats is received, and the
received data seems to be a parity error.
Smaller than 7-Receiver Clock Length
16
Start bit Length
Mode
Operation
The short start bit is ignored. (Normal)
Smaller than 31-Receiver Clock Length
64
8-Receiver Clock Length
16
The short start bit is ignored. (Normal)
Data cannot be received correctly due to a malfunction.
32-Receiver Clock Length
64
Data cannot be received correctly due to a malfunction.
9 to 16-Receiver Clock Length
16
The bit is regarded as a start bit. (normal)
33 to 64-Receiver Clock Length
64
The bit is regarded as a start bit. (normal)
相關(guān)PDF資料
PDF描述
MSM82C53-2GS-K 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
MSM82C53-2RS 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24
MSM82C53-2GS 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
MSM82C53-2JS 3 TIMER(S), PROGRAMMABLE TIMER, PQCC28
MSM82C55A-2GS-2K 24 I/O, PIA-GENERAL PURPOSE, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM82C51A-2JS 制造商:ROHM Semiconductor 功能描述:
MSM82C51A-2RS 制造商:ROHM Semiconductor 功能描述: 制造商:ROHM Semiconductor 功能描述:USART,Programmable multifunction 制造商:ROHM Semiconductor 功能描述:USART, programmable multi-function communication interface
MSM82C53-2 GS-K 制造商:ROHM Semiconductor 功能描述:
MSM82C53-2GS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:CMOS PROGRAMMABLE INTERVAL TIMER
MSM82C53-2JS 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:CMOS PROGRAMMABLE INTERVAL TIMER
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