參數(shù)資料
型號(hào): MSM82C51A-2JS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PQCC28
封裝: PLASTIC, QFJ-28
文件頁數(shù): 6/26頁
文件大?。?/td> 188K
代理商: MSM82C51A-2JS
14/26
Semiconductor
MSM82C51A-2RS/GS/JS
Serial Interface Part
Notes: 1. AC characteristics are measured at 150 pF capacity load as an output load based on 0.8 V at
low level and 2.2 V at high level for output and 1.5 V for input.
2. Addresses are CS and C/D.
3. fTX or fRX 1/(30 Tcy) 1 Baud
fTX or fRX 1/(5 Tcy)
16, 64 Baud
4. This recovery time is mode Initialization only. Recovery time between command writes for
Asynchronous Mode is 8 tCY and for Synchronous Mode is 18 tCY.
Write Data is allowed only when TXRDY = 1.
5. This recovery time is Status read only.
Read Data is allowed only when RXRDY = 1.
6. Status update can have a maximum delay of 28 clock periods from event affecting the status.
Max.
Main Clock Period
tCY
ns
Parameter
Unit
Symbol
Min.
160
Note 3
Remarks
Clock Low Tme
tf
ns
Clock High Time
tf
tCY –50
ns
50
70
Clock Rise/Fall Time
tr, tf
20
ns
TXD Delay from Falling Edge of TXC
tDTX
1
mS
Transmitter Clock Frequency
fTX
64
kHz
fTX
615
kHz
DC
Note 3
fTX
615
kHz
DC
1 Baud
16 Baud
64 Baud
Transmitter Clock Low Time
tTPW
tCY
1 Baud
tTPW
tCY
Transmitter Clock High Time
tTPD
13
2
15
tCY
16 , 64 Baud
1 Baud
tTPD
tCY
3
16 , 64 Baud
Receiver Clock Frequency
fRX
64
DC
kHz
1 Baud
fRX
615
kHz
fRX
615
kHz
DC
16 Baud
64 Baud
Note 3
Receiver Clock Low Time
tRPW
tCY
13
tRPW
tCY
2
1 Baud
16 , 64 Baud
Receiver Clock High Time
tRPD
tCY
tRPD
tCY
15
3
1 Baud
16 , 64 Baud
Time from the Center of Last Bit to the Rise of
TXRDY
tTXRDY
8
tCY
Time from the Leading Edge of WR to the Fall
of TXRDY
tTXRDY CLEAR
400
ns
Time From the Center of Last Bit to the Rise of RXRDY
tRXRDY
26
tCY
Time from the Leading Edge of RD to the Fall
of RXRDY
tRXRDY CLEAR
400
ns
Internal SYNDET Delay Time from Rising Edge of RXC
tIS
26
tCY
MODEM Control Signal Delay Time from Rising Edge
of WR
tWC
tCY
8
MODEM Control Signal Setup Time for Falling Edge
of RD
tCR
tCY
20
RXD Setup Time for Rising Edge of RXC (1X Baud)
tRXDS
tCY
11
RXD Hold Time for Falling Edge of RXC (1X Baud)
tRXDH
tCY
17
SYNDET Setup Time for RXC
tES
tCY
18
TXE Delay Time from the Center of Last Bit
tTXEMPTY
tCY
20
(VCC = 4.5 to 5.5 V, Ta = –40 to 85°C)
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