參數(shù)資料
型號: MSM82C53-2RS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24
封裝: 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-24
文件頁數(shù): 3/19頁
文件大?。?/td> 139K
代理商: MSM82C53-2RS
11/19
Semiconductor
MSM82C53-2RS/GS/JS
Mode Definition
Mode 0 (terminal count)
The counter output is set to “L” level by the mode setting. If the count value is then written
in the counter with the gate input at “H” level (that is, upon completion of writing the MSB
when there are two bytes), the clock input counting is started. When the terminal count is
reached, the output is switched to “H” level and is maintained in this status until the control
word and count value are set again.
Counting is interrupted if the gate input is switched to “L” level, and restarted when switched
back to “H” level.
When Count Values are written during counting, the operation is as follows:
1-byte Read/Load. ............ When the new count value is written, counting is stopped
immediately, and then restarted at the new count value by the next
clock.
2-byte Read/Load ............. When byte 1 (LSB) of the new count value is written, counting is
stopped immediately. Counting is restarted at the new count
value when byte 2 (MSB) is written.
Mode 1 (programmable one-shot)
The counter output is switched to “H” level by the mode setting. Note that in this mode,
counting is not started if only the count value is written. Since counting has to be started in
this mode by using the leading edge of the gate input as a trigger, the counter output is
switched to “L” level by the next clock after the gate input trigger. This “L” level status is
maintained during the set count value, and is switched back to “H” level when the terminal
count is reached.
Once counting has been started, there is no interruption until the terminal count is reached,
even if the gate input is switched to “L” level in the meantime. And although counting
continues even if a new count value is written during the counting, counting is started at the
new count value if another trigger is applied by the gate input.
Mode 2 (rate generator)
The counter output is switched to “H” level by the mode setting. When the gate input is at
“H” level, counting is started by the next clock after the count value has been written. And
if the gate input is at “L” level, counting is started by using the rising edge of the gate input
as a trigger after the count value has been set.
An “L” level output pulse appears at the counter output during a single clock duration once
every n clock inputs where n is the set count value. If a new count value is written during
while counting is in progress, counting is started at the new count value following output of
the pulse currently being counted. And if the gate input is switched to “L” level during
counting, the counter output is forced to switch to “H” level, the counting being restarted by
the rising edge of the gate input.
Mode 3 (square waveform rate generator)
The counter output is switched to “H” level by the mode setting. Counting is started in the
same way as described for mode 2 above.
The repeated square wave output appearing at the counter output contains half the number
of counts as the set count value. If the set count value (n) is an odd number, the repeated square
wave output consists of only (n+1)/2 clock inputs at “H” level and (n-1)/2 clock inputs at “L”
level.
If a new count value is written during counting, the new count value is reflected immediately
after the change (“H” to “L” or “L” to “H”) in the next counter output to be executed. The
counting operation at the gate input is done the same as in mode 2.
相關(guān)PDF資料
PDF描述
MSM82C53-2GS 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
MSM82C53-2JS 3 TIMER(S), PROGRAMMABLE TIMER, PQCC28
MSM82C55A-2GS-2K 24 I/O, PIA-GENERAL PURPOSE, PQFP44
MSM82C55A-2RS 24 I/O, PIA-GENERAL PURPOSE, PDIP40
MSM82C55A-2VJS 24 I/O, PIA-GENERAL PURPOSE, PQCC44
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